Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology - Karol Kalna (IEEE Transactions on Electron Devices, 2016)
The device and circuit performance of InGaAs and Ge hybrid CMOS with a gate length of 20 nm using an implant free quantum well (QW) device architecture is evaluated using a multi-scale methodology by ensemble Monte Carlo simulation, drift-diffusion simulation, compact modeling, and TCAD mixed-mode circuit simulation. We report that the QW and doped substrate of the hybrid CMOS help to reduce short channel effects (SCE) by enhanced carrier confinement. The QW architecture reduces the negative impact of a low density of states in III-V materials. In addition, the calculated access resistance is found to be a much lower than in Si counterparts thanks to a heavily doped overgrowth source/drain contact. We predict an overall low gate capacitance and a large drive current when compared with Si-CMOS that leads to a significant reduction in a circuit propagation time delay (5.5 ps).