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A parallel implementation of sequential minimal optimization on FPGA

Daniel H. Noronha, Matheus Torquato Orcid Logo, Marcelo A.C. Fernandes

Microprocessors and Microsystems, Volume: 69, Pages: 138 - 151

Swansea University Author: Matheus Torquato Orcid Logo

Abstract

This paper proposes a parallel FPGA implementation of the training phase of a Support Vector Machine (SVM). The training phase of the SVM is implemented using Sequential Minimal Optimization (SMO), which enables the resolution of a complex convex optimization problem using simple steps. The SMO impl...

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Published in: Microprocessors and Microsystems
ISSN: 0141-9331
Published: 2019
Online Access: Check full text

URI: https://cronfa.swan.ac.uk/Record/cronfa50890
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Abstract: This paper proposes a parallel FPGA implementation of the training phase of a Support Vector Machine (SVM). The training phase of the SVM is implemented using Sequential Minimal Optimization (SMO), which enables the resolution of a complex convex optimization problem using simple steps. The SMO implementation is also highly parallel and uses some acceleration techniques, such as the error cache. Moreover, the Hardware Friendly Kernel (HFK) is used in order to reduce the kernel’s area, enabling an increase in the number of kernels per area. After the parallel implementation in hardware, the SVM is validated by bit-accurate simulation. Finally, analysis associated with the temporal performance of the proposed structure, as well as analysis associated with FPGAs area usage is performed.
Keywords: SVM, SMO, FPGA, Support vector machine, Sequential minimal optimization, Hardware
College: Faculty of Science and Engineering
Start Page: 138
End Page: 151