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Conference Paper/Proceeding/Abstract 1276 views 369 downloads

General hardware multicasting for fine-grained message-passing architectures

Matthew Naylor, Simon W. Moore, David Thomas, Jonathan R. Beaumont, Shane Fleming, Mark Vousden, A. Theodore Markettos, Thomas Bytheway, Andrew Brown

2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), Pages: 126 - 133

Swansea University Author: Shane Fleming

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DOI (Published version): 10.1109/pdp52278.2021.00028

Abstract

Manycore architectures are increasingly favouring message-passing or partitioned global address spaces (PGAS) over cache coherency for reasons of power efficiency and scalability. However, in the absence of cache coherency, there can be a lack of hardware support for one-to-many communication patter...

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Published in: 2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)
ISBN: 978-1-6654-4764-5 978-1-6654-1455-5
ISSN: 1066-6192 2377-5750
Published: IEEE 2021
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URI: https://cronfa.swan.ac.uk/Record/cronfa56452
Abstract: Manycore architectures are increasingly favouring message-passing or partitioned global address spaces (PGAS) over cache coherency for reasons of power efficiency and scalability. However, in the absence of cache coherency, there can be a lack of hardware support for one-to-many communication patterns, which are prevalent in someapplication domains. To address this, we present new hardware primitives for multicast communication in rack-scale manycore systems. These primitives guarantee delivery to both colocated and distributed destinations, and can capture large unstructured communication patterns precisely. As a result, reliable multicast transfers among any number of software tasks, connected in any topology, can be fully offloaded to hardware. We implement the new primitives in a research platform consisting of 50K RISC-V threads distributed over 48 FPGAs, and demonstrate significant performance benefits on a range of applications expressed using a high-level vertex-centric programming model.
Keywords: Scalability, Computer architecture, Multicast communication, System recovery, Hardware, Software, Topology
College: Faculty of Science and Engineering
Funders: This work was supported by UK EPSRC grant EP/N031768/1 (POETS project).
Start Page: 126
End Page: 133

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