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E-Thesis 249 views

Development And Investigation Of A Novel Dry Etch Silicon Smoothing Process / ROLAND MUMFORD

Swansea University Author: ROLAND MUMFORD

  • Redacted version - open access under embargo until: 11th September 2027

DOI (Published version): 10.23889/SUthesis.68269

Abstract

This thesis describes the development of a dry plasma etch smoothing technique to replace the conventional Chemical Mechanical Polishing process within a device manufacturing scheme in the semiconductor industry. An important semiconductor manufacturing process is 3D wafer packaging, which allows ve...

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Published: Swansea, Wales, UK 2024
Institution: Swansea University
Degree level: Doctoral
Degree name: Ph.D
Supervisor: Guy, Owen J. ; Elwin, Matt
URI: https://cronfa.swan.ac.uk/Record/cronfa68269
first_indexed 2025-01-30T16:02:05Z
last_indexed 2025-06-07T05:05:12Z
id cronfa68269
recordtype RisThesis
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spelling 2025-06-06T12:42:45.3335599 v2 68269 2024-11-14 Development And Investigation Of A Novel Dry Etch Silicon Smoothing Process 69d45b694e1e475467e6c0c80de3a02e ROLAND MUMFORD ROLAND MUMFORD true false 2024-11-14 This thesis describes the development of a dry plasma etch smoothing technique to replace the conventional Chemical Mechanical Polishing process within a device manufacturing scheme in the semiconductor industry. An important semiconductor manufacturing process is 3D wafer packaging, which allows vertical stacking of wafer die. 3D wafer packing represents a significant component of the total wafer level processing cost. A critical step in the 3D packaging process flow is the Chemical Mechanical Polishing process. Replacement of the CMP process step with a corresponding dry etch can yield significant time and cost savings. This is achievable through reductions in metrology and wafer handling requirements and lower volumes of materials needed for plasma-etch based processes compared with CMP. Incorporating equipment already utilized in the 3D integrated wafer packaging process during the subsequent Through Silicon Via (TSV) reveal step, process efficiencies can be achieved, with overall die yields being maintained. Using dry etch technology to treat a 200 nm rough back-ground silicon surface, a smooth surface with a peak to valley roughness of less than 6 nm is demonstrated, which is comparable to a virgin silicon wafer. This patented process differs from other dry etch smoothing techniques in that it aims to eliminate any visual grind marks rather than just reducing the surface roughness. The elimination of visible grind marks is critical in later optical inspection where these surface scratches are falsely identified as defects. The quality of the plasma polished surface is equivalent to that of a CMP processed wafer and as such, this process has been implemented in manufacturing replacing the CMP step. The novel process described combines a surface modification process followed by a roughness reduction iteratively, to produce a smooth surface without visible grind marks. Further work describes the application of the smoothing process to microneedles, with the aim of improving the process flow. Smoothing of silicon carbide has been performed. Finally, an extension of the TSV reveal process is described, called extreme thinning, with the development of a predictive model to minimize final total thickness variation. Silicon smoothing can also be beneficial to this application. E-Thesis Swansea, Wales, UK 11 9 2024 2024-09-11 10.23889/SUthesis.68269 A selection of third party content is partially redacted from this thesis due to copyright restrictions.ORCiD identifier: https://orcid.org/0000-0002-5081-1851 COLLEGE NANME COLLEGE CODE Swansea University Guy, Owen J. ; Elwin, Matt Doctoral Ph.D SPTS Technologies SPTS Technologies 2025-06-06T12:42:45.3335599 2024-11-14T11:30:26.7619649 Faculty of Science and Engineering School of Engineering and Applied Sciences - Chemistry ROLAND MUMFORD 1 Under embargo Under embargo 2025-06-05T16:07:06.9468729 Output 32286859 application/pdf Redacted version - open access true 2027-09-11T00:00:00.0000000 Copyright: The Author, Roland Mumford, 2024. true eng
title Development And Investigation Of A Novel Dry Etch Silicon Smoothing Process
spellingShingle Development And Investigation Of A Novel Dry Etch Silicon Smoothing Process
ROLAND MUMFORD
title_short Development And Investigation Of A Novel Dry Etch Silicon Smoothing Process
title_full Development And Investigation Of A Novel Dry Etch Silicon Smoothing Process
title_fullStr Development And Investigation Of A Novel Dry Etch Silicon Smoothing Process
title_full_unstemmed Development And Investigation Of A Novel Dry Etch Silicon Smoothing Process
title_sort Development And Investigation Of A Novel Dry Etch Silicon Smoothing Process
author_id_str_mv 69d45b694e1e475467e6c0c80de3a02e
author_id_fullname_str_mv 69d45b694e1e475467e6c0c80de3a02e_***_ROLAND MUMFORD
author ROLAND MUMFORD
author2 ROLAND MUMFORD
format E-Thesis
publishDate 2024
institution Swansea University
doi_str_mv 10.23889/SUthesis.68269
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Engineering and Applied Sciences - Chemistry{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Engineering and Applied Sciences - Chemistry
document_store_str 0
active_str 0
description This thesis describes the development of a dry plasma etch smoothing technique to replace the conventional Chemical Mechanical Polishing process within a device manufacturing scheme in the semiconductor industry. An important semiconductor manufacturing process is 3D wafer packaging, which allows vertical stacking of wafer die. 3D wafer packing represents a significant component of the total wafer level processing cost. A critical step in the 3D packaging process flow is the Chemical Mechanical Polishing process. Replacement of the CMP process step with a corresponding dry etch can yield significant time and cost savings. This is achievable through reductions in metrology and wafer handling requirements and lower volumes of materials needed for plasma-etch based processes compared with CMP. Incorporating equipment already utilized in the 3D integrated wafer packaging process during the subsequent Through Silicon Via (TSV) reveal step, process efficiencies can be achieved, with overall die yields being maintained. Using dry etch technology to treat a 200 nm rough back-ground silicon surface, a smooth surface with a peak to valley roughness of less than 6 nm is demonstrated, which is comparable to a virgin silicon wafer. This patented process differs from other dry etch smoothing techniques in that it aims to eliminate any visual grind marks rather than just reducing the surface roughness. The elimination of visible grind marks is critical in later optical inspection where these surface scratches are falsely identified as defects. The quality of the plasma polished surface is equivalent to that of a CMP processed wafer and as such, this process has been implemented in manufacturing replacing the CMP step. The novel process described combines a surface modification process followed by a roughness reduction iteratively, to produce a smooth surface without visible grind marks. Further work describes the application of the smoothing process to microneedles, with the aim of improving the process flow. Smoothing of silicon carbide has been performed. Finally, an extension of the TSV reveal process is described, called extreme thinning, with the development of a predictive model to minimize final total thickness variation. Silicon smoothing can also be beneficial to this application.
published_date 2024-09-11T07:25:23Z
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score 11.08895

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