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High-Performance Parallel Implementation of Genetic Algorithm on FPGA

Matheus Torquato Orcid Logo, Marcelo A. C. Fernandes

Circuits, Systems, and Signal Processing, Volume: 38, Issue: 9, Pages: 4014 - 4039

Swansea University Author: Matheus Torquato Orcid Logo

Abstract

Genetic algorithms (GAs) are used to solve search and optimization problems in which an optimal solution can be found using an iterative process with probabilistic and non-deterministic transitions. However, depending on the problem’s nature, the time required to find a solution can be high in seque...

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Published in: Circuits, Systems, and Signal Processing
ISSN: 0278-081X 1531-5878
Published: 2019
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URI: https://cronfa.swan.ac.uk/Record/cronfa49021
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fullrecord <?xml version="1.0"?><rfc1807><datestamp>2019-04-11T11:52:09.7761703</datestamp><bib-version>v2</bib-version><id>49021</id><entry>2019-02-28</entry><title>High-Performance Parallel Implementation of Genetic Algorithm on FPGA</title><swanseaauthors><author><sid>7a053c668886b4642286baed36fdba90</sid><ORCID>0000-0001-6356-3538</ORCID><firstname>Matheus</firstname><surname>Torquato</surname><name>Matheus Torquato</name><active>true</active><ethesisStudent>false</ethesisStudent></author></swanseaauthors><date>2019-02-28</date><deptcode>SCS</deptcode><abstract>Genetic algorithms (GAs) are used to solve search and optimization problems in which an optimal solution can be found using an iterative process with probabilistic and non-deterministic transitions. However, depending on the problem&#x2019;s nature, the time required to find a solution can be high in sequential machines due to the computational complexity of genetic algorithms. This work proposes a full-parallel implementation of a genetic algorithm on field-programmable gate array (FPGA). Optimization of the system&#x2019;s processing time is the main goal of this project. Results associated with the processing time and area occupancy (on FPGA) for various population sizes are analyzed. Studies concerning the accuracy of the GA response for the optimization of two variables functions were also evaluated for the hardware implementation. However, the high-performance implementation proposed in this paper is able to work with more variable from some adjustments on hardware architecture. The results showed that the GA full-parallel implementation achieved throughput about 16 millions of generations per second and speedups between 17 and 170,000 associated with several works proposed in the literature.</abstract><type>Journal Article</type><journal>Circuits, Systems, and Signal Processing</journal><volume>38</volume><journalNumber>9</journalNumber><paginationStart>4014</paginationStart><paginationEnd>4039</paginationEnd><publisher/><issnPrint>0278-081X</issnPrint><issnElectronic>1531-5878</issnElectronic><keywords>Parallel implementation, FPGA, Genetic algorithms, Reconfigurable computing</keywords><publishedDay>30</publishedDay><publishedMonth>9</publishedMonth><publishedYear>2019</publishedYear><publishedDate>2019-09-30</publishedDate><doi>10.1007/s00034-019-01037-w</doi><url/><notes/><college>COLLEGE NANME</college><department>Computer Science</department><CollegeCode>COLLEGE CODE</CollegeCode><DepartmentCode>SCS</DepartmentCode><institution>Swansea University</institution><apcterm/><lastEdited>2019-04-11T11:52:09.7761703</lastEdited><Created>2019-02-28T14:11:33.2762286</Created><authors><author><firstname>Matheus</firstname><surname>Torquato</surname><orcid>0000-0001-6356-3538</orcid><order>1</order></author><author><firstname>Marcelo A. C.</firstname><surname>Fernandes</surname><order>2</order></author></authors><documents><document><filename>0049021-19032019102729.pdf</filename><originalFilename>torquato2019.pdf</originalFilename><uploaded>2019-03-19T10:27:29.9970000</uploaded><type>Output</type><contentLength>664952</contentLength><contentType>application/pdf</contentType><version>Accepted Manuscript</version><cronfaStatus>true</cronfaStatus><embargoDate>2020-01-21T00:00:00.0000000</embargoDate><copyrightCorrect>true</copyrightCorrect><language>eng</language></document></documents><OutputDurs/></rfc1807>
spelling 2019-04-11T11:52:09.7761703 v2 49021 2019-02-28 High-Performance Parallel Implementation of Genetic Algorithm on FPGA 7a053c668886b4642286baed36fdba90 0000-0001-6356-3538 Matheus Torquato Matheus Torquato true false 2019-02-28 SCS Genetic algorithms (GAs) are used to solve search and optimization problems in which an optimal solution can be found using an iterative process with probabilistic and non-deterministic transitions. However, depending on the problem’s nature, the time required to find a solution can be high in sequential machines due to the computational complexity of genetic algorithms. This work proposes a full-parallel implementation of a genetic algorithm on field-programmable gate array (FPGA). Optimization of the system’s processing time is the main goal of this project. Results associated with the processing time and area occupancy (on FPGA) for various population sizes are analyzed. Studies concerning the accuracy of the GA response for the optimization of two variables functions were also evaluated for the hardware implementation. However, the high-performance implementation proposed in this paper is able to work with more variable from some adjustments on hardware architecture. The results showed that the GA full-parallel implementation achieved throughput about 16 millions of generations per second and speedups between 17 and 170,000 associated with several works proposed in the literature. Journal Article Circuits, Systems, and Signal Processing 38 9 4014 4039 0278-081X 1531-5878 Parallel implementation, FPGA, Genetic algorithms, Reconfigurable computing 30 9 2019 2019-09-30 10.1007/s00034-019-01037-w COLLEGE NANME Computer Science COLLEGE CODE SCS Swansea University 2019-04-11T11:52:09.7761703 2019-02-28T14:11:33.2762286 Matheus Torquato 0000-0001-6356-3538 1 Marcelo A. C. Fernandes 2 0049021-19032019102729.pdf torquato2019.pdf 2019-03-19T10:27:29.9970000 Output 664952 application/pdf Accepted Manuscript true 2020-01-21T00:00:00.0000000 true eng
title High-Performance Parallel Implementation of Genetic Algorithm on FPGA
spellingShingle High-Performance Parallel Implementation of Genetic Algorithm on FPGA
Matheus Torquato
title_short High-Performance Parallel Implementation of Genetic Algorithm on FPGA
title_full High-Performance Parallel Implementation of Genetic Algorithm on FPGA
title_fullStr High-Performance Parallel Implementation of Genetic Algorithm on FPGA
title_full_unstemmed High-Performance Parallel Implementation of Genetic Algorithm on FPGA
title_sort High-Performance Parallel Implementation of Genetic Algorithm on FPGA
author_id_str_mv 7a053c668886b4642286baed36fdba90
author_id_fullname_str_mv 7a053c668886b4642286baed36fdba90_***_Matheus Torquato
author Matheus Torquato
author2 Matheus Torquato
Marcelo A. C. Fernandes
format Journal article
container_title Circuits, Systems, and Signal Processing
container_volume 38
container_issue 9
container_start_page 4014
publishDate 2019
institution Swansea University
issn 0278-081X
1531-5878
doi_str_mv 10.1007/s00034-019-01037-w
document_store_str 1
active_str 0
description Genetic algorithms (GAs) are used to solve search and optimization problems in which an optimal solution can be found using an iterative process with probabilistic and non-deterministic transitions. However, depending on the problem’s nature, the time required to find a solution can be high in sequential machines due to the computational complexity of genetic algorithms. This work proposes a full-parallel implementation of a genetic algorithm on field-programmable gate array (FPGA). Optimization of the system’s processing time is the main goal of this project. Results associated with the processing time and area occupancy (on FPGA) for various population sizes are analyzed. Studies concerning the accuracy of the GA response for the optimization of two variables functions were also evaluated for the hardware implementation. However, the high-performance implementation proposed in this paper is able to work with more variable from some adjustments on hardware architecture. The results showed that the GA full-parallel implementation achieved throughput about 16 millions of generations per second and speedups between 17 and 170,000 associated with several works proposed in the literature.
published_date 2019-09-30T03:59:46Z
_version_ 1763753052194471936
score 11.012678