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Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder

Maria G. F. Coutinho, Matheus Torquato Orcid Logo, Marcelo A. C. Fernandes

IEEE Access, Pages: 1 - 1

Swansea University Author: Matheus Torquato Orcid Logo

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DOI (Published version): 10.1109/ACCESS.2019.2907261

Abstract

Deep learning techniques have been gaining prominence in the research world in the past years, however, the deep learning algorithms have high computational cost, making them hard to be used to several commercial applications. On the other hand, new alternatives have been studied and some methodolog...

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Published in: IEEE Access
ISSN: 2169-3536
Published: 2019
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URI: https://cronfa.swan.ac.uk/Record/cronfa49874
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Abstract: Deep learning techniques have been gaining prominence in the research world in the past years, however, the deep learning algorithms have high computational cost, making them hard to be used to several commercial applications. On the other hand, new alternatives have been studied and some methodologies focusing on accelerating complex algorithms including those based on reconfigurable hardware has been showing significant results. Therefore, the objective of this work is to propose a neural network hardware implementation to be used in deep learning applications. The implementation was developed on a Field Programmable Gate Array (FPGA) and supports Deep Neural Network (DNN) trained with the Stacked Sparse Autoencoder (SSAE) technique. In order to allow DNNs with several inputs and layers on the FPGA, the systolic array technique was used in the entire architecture. Details regarding the designed implementation were evidenced, as well as the hardware area occupation in and the processing time for two different implementations. The results showed that both implementations achieved high throughput enabling Deep Learning techniques to be applied for problems with large data amounts.
College: Faculty of Science and Engineering
Start Page: 1
End Page: 1

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