A Hardware Descriptive Approach to Beetle Antennae Search

Yue, Zongcheng; Li, Gang; Jiang, Xiangyuan; Li, Shuai; Cheng, Jian; Ren, Peng

doi:10.1109/access.2020.2993600

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A Hardware Descriptive Approach to Beetle Antennae Search

Zongcheng Yue, Gang Li, Xiangyuan Jiang, Shuai Li

, Jian Cheng, Peng Ren

IEEE Access, Volume: 8, Pages: 89059 - 89070

Swansea University Author: Shuai Li

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DOI (Published version): 10.1109/access.2020.2993600

Abstract

Beetle antennae search (BAS) is a newly developed meta-heuristic algorithm which is effectively used for optimizing objective functions of complex forms or even unknown forms. The common practice for implementing meta-heuristic algorithms including the BAS largely relies on programming in a high-lev...

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Published in:	IEEE Access
ISSN:	2169-3536
Published:	Institute of Electrical and Electronics Engineers (IEEE) 2020
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first_indexed	2020-06-11T13:09:02Z
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spelling	2020-07-22T14:07:04.1408921 v2 54434 2020-06-11 A Hardware Descriptive Approach to Beetle Antennae Search 42ff9eed09bcd109fbbe484a0f99a8a8 0000-0001-8316-5289 Shuai Li Shuai Li true false 2020-06-11 MECH Beetle antennae search (BAS) is a newly developed meta-heuristic algorithm which is effectively used for optimizing objective functions of complex forms or even unknown forms. The common practice for implementing meta-heuristic algorithms including the BAS largely relies on programming in a high-level language and executing the code on a computer platform. However, the high-level implementation of the BAS algorithm hinders it from being used in an embedding system, where real-time operations are normally required. To address this limitation, we present an approach to implementing the BAS algorithm on a field-programmable gate array (FPGA). Specifically, we program the BAS function in the Verilog hardware description language (HDL), which provides a tractable vehicle for implementing the BAS algorithm at the gate level on the FPGA chip. We simulate our Verilog HDL based BAS module with the Modelsim platform. Simulation results validate the feasibility of our proposed Verilog HDL implementation of the BAS. Additionally, we implement the BAS model on the Zynq XC7Z010 platform, with 132.5 μ s latency for model implementation. Journal Article IEEE Access 8 89059 89070 Institute of Electrical and Electronics Engineers (IEEE) 2169-3536 22 5 2020 2020-05-22 10.1109/access.2020.2993600 COLLEGE NANME Mechanical Engineering COLLEGE CODE MECH Swansea University 2020-07-22T14:07:04.1408921 2020-06-11T10:34:47.5674373 Zongcheng Yue 1 Gang Li 2 Xiangyuan Jiang 3 Shuai Li 0000-0001-8316-5289 4 Jian Cheng 5 Peng Ren 6 54434__17469__3b6ec479597349749cf9702529566c37.pdf 54434.pdf 2020-06-11T10:37:10.8242485 Output 2733369 application/pdf Version of Record true This work is licensed under a Creative Commons Attribution 4.0 License true http://creativecommons.org/licenses/by/4.0/
title	A Hardware Descriptive Approach to Beetle Antennae Search
spellingShingle	A Hardware Descriptive Approach to Beetle Antennae Search Shuai Li
title_short	A Hardware Descriptive Approach to Beetle Antennae Search
title_full	A Hardware Descriptive Approach to Beetle Antennae Search
title_fullStr	A Hardware Descriptive Approach to Beetle Antennae Search
title_full_unstemmed	A Hardware Descriptive Approach to Beetle Antennae Search
title_sort	A Hardware Descriptive Approach to Beetle Antennae Search
author_id_str_mv	42ff9eed09bcd109fbbe484a0f99a8a8
author_id_fullname_str_mv	42ff9eed09bcd109fbbe484a0f99a8a8_***_Shuai Li
author	Shuai Li
author2	Zongcheng Yue Gang Li Xiangyuan Jiang Shuai Li Jian Cheng Peng Ren
format	Journal article
container_title	IEEE Access
container_volume	8
container_start_page	89059
publishDate	2020
institution	Swansea University
issn	2169-3536
doi_str_mv	10.1109/access.2020.2993600
publisher	Institute of Electrical and Electronics Engineers (IEEE)
document_store_str	1
active_str	0
description	Beetle antennae search (BAS) is a newly developed meta-heuristic algorithm which is effectively used for optimizing objective functions of complex forms or even unknown forms. The common practice for implementing meta-heuristic algorithms including the BAS largely relies on programming in a high-level language and executing the code on a computer platform. However, the high-level implementation of the BAS algorithm hinders it from being used in an embedding system, where real-time operations are normally required. To address this limitation, we present an approach to implementing the BAS algorithm on a field-programmable gate array (FPGA). Specifically, we program the BAS function in the Verilog hardware description language (HDL), which provides a tractable vehicle for implementing the BAS algorithm at the gate level on the FPGA chip. We simulate our Verilog HDL based BAS module with the Modelsim platform. Simulation results validate the feasibility of our proposed Verilog HDL implementation of the BAS. Additionally, we implement the BAS model on the Zynq XC7Z010 platform, with 132.5 μ s latency for model implementation.
published_date	2020-05-22T04:07:58Z
_version_	1763753568452476928
score	11.036334

A Hardware Descriptive Approach to Beetle Antennae Search

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