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A Hardware Descriptive Approach to Beetle Antennae Search

Zongcheng Yue, Gang Li, Xiangyuan Jiang, Shuai Li Orcid Logo, Jian Cheng, Peng Ren

IEEE Access, Volume: 8, Pages: 89059 - 89070

Swansea University Author: Shuai Li Orcid Logo

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DOI (Published version): 10.1109/access.2020.2993600

Abstract

Beetle antennae search (BAS) is a newly developed meta-heuristic algorithm which is effectively used for optimizing objective functions of complex forms or even unknown forms. The common practice for implementing meta-heuristic algorithms including the BAS largely relies on programming in a high-lev...

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Published in: IEEE Access
ISSN: 2169-3536
Published: Institute of Electrical and Electronics Engineers (IEEE) 2020
Online Access: Check full text

URI: https://cronfa.swan.ac.uk/Record/cronfa54434
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Abstract: Beetle antennae search (BAS) is a newly developed meta-heuristic algorithm which is effectively used for optimizing objective functions of complex forms or even unknown forms. The common practice for implementing meta-heuristic algorithms including the BAS largely relies on programming in a high-level language and executing the code on a computer platform. However, the high-level implementation of the BAS algorithm hinders it from being used in an embedding system, where real-time operations are normally required. To address this limitation, we present an approach to implementing the BAS algorithm on a field-programmable gate array (FPGA). Specifically, we program the BAS function in the Verilog hardware description language (HDL), which provides a tractable vehicle for implementing the BAS algorithm at the gate level on the FPGA chip. We simulate our Verilog HDL based BAS module with the Modelsim platform. Simulation results validate the feasibility of our proposed Verilog HDL implementation of the BAS. Additionally, we implement the BAS model on the Zynq XC7Z010 platform, with 132.5 μ s latency for model implementation.
Start Page: 89059
End Page: 89070

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