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General Integration of Vertical Nanowire Arrays with Silicon for Highly Parallel Electronic Device Applications

, Jon E. Evans, Alex Lord Orcid Logo, Nathan A. Smith, Michael B. Ward, Steve Wilks

The Journal of Physical Chemistry C, Volume: 122, Issue: 43, Pages: 24716 - 24724

Swansea University Authors: , , , Alex Lord Orcid Logo, Steve Wilks

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DOI (Published version): 10.1021/acs.jpcc.8b06757

Abstract

Near-term commercialization of nanowire-based devices is possible through an integrative approach with existing semiconductor platforms. Research-based single nanowire devices suffer from issues related to size dependence and variability; hence, the use of a large number of nanowires in parallel is...

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Published in: The Journal of Physical Chemistry C
ISSN: 1932-7447 1932-7455
Published: 2018
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URI: https://cronfa.swan.ac.uk/Record/cronfa45500
first_indexed 2019-07-17T21:23:32Z
last_indexed 2019-07-17T21:23:32Z
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spelling 2019-02-12T14:47:28.4948582 v2 45500 2018-11-08 General Integration of Vertical Nanowire Arrays with Silicon for Highly Parallel Electronic Device Applications 969d56ddd96f1b63ceada307937e85cf true false 095f58c4e9920a5cc6baa1f897774f22 true false 61dee2a219f268bb2e91ba8f71b0f536 true false d547bad707e12f5a9f12d4fcbeea87ed 0000-0002-6258-2187 Alex Lord Alex Lord true false 948a547e27d969b7e192b4620688704d Steve Wilks Steve Wilks true false 2018-11-08 Near-term commercialization of nanowire-based devices is possible through an integrative approach with existing semiconductor platforms. Research-based single nanowire devices suffer from issues related to size dependence and variability; hence, the use of a large number of nanowires in parallel is a prerequisite for real-world devices to scale output and provide statistical averaging of properties. Parallel integration is most directly achieved through electrical contacting of nanowire arrays in the as-grown vertical configuration. Here, we demonstrate a one-step process that overcomes several technological barriers simultaneously, allowing the seamless electrical integration of ZnO nanowire arrays with industry standard silicon substrates. Our seamless integration process is based on the deposition of a metal contact layer on silicon and subsequent CVD nanowire growth. Combined SEM, XRD, and TEM measurements show compositional and structural changes to each metal contact layer candidate during the high-temperature growth process, directly influencing the ZnO base growth and controlling the properties and dimensions of the resulting nanowire arrays. Findings were correlated to nanoscale multiprobe electrical measurements of individual nanowires in the vertical device configuration to demonstrate the effects of each metal layer on conduction through the nanowires and the metal–semiconductor interface. The refractory metal molybdenum gave highly aligned, dense nanowire growth and formed a low-resistance ohmic contact to the base of these arrays offering a simple and scalable process-ready solution for integrating nanowires with the industry standard silicon platform. Journal Article The Journal of Physical Chemistry C 122 43 24716 24724 1932-7447 1932-7455 31 12 2018 2018-12-31 10.1021/acs.jpcc.8b06757 COLLEGE NANME COLLEGE CODE Swansea University 2019-02-12T14:47:28.4948582 2018-11-08T10:39:56.6614482 Faculty of Science and Engineering School of Engineering and Applied Sciences - Uncategorised 1 Jon E. Evans 2 Alex Lord 0000-0002-6258-2187 3 Nathan A. Smith 4 Michael B. Ward 5 Steve Wilks 6
title General Integration of Vertical Nanowire Arrays with Silicon for Highly Parallel Electronic Device Applications
spellingShingle General Integration of Vertical Nanowire Arrays with Silicon for Highly Parallel Electronic Device Applications



Alex Lord
Steve Wilks
title_short General Integration of Vertical Nanowire Arrays with Silicon for Highly Parallel Electronic Device Applications
title_full General Integration of Vertical Nanowire Arrays with Silicon for Highly Parallel Electronic Device Applications
title_fullStr General Integration of Vertical Nanowire Arrays with Silicon for Highly Parallel Electronic Device Applications
title_full_unstemmed General Integration of Vertical Nanowire Arrays with Silicon for Highly Parallel Electronic Device Applications
title_sort General Integration of Vertical Nanowire Arrays with Silicon for Highly Parallel Electronic Device Applications
author_id_str_mv 969d56ddd96f1b63ceada307937e85cf
095f58c4e9920a5cc6baa1f897774f22
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095f58c4e9920a5cc6baa1f897774f22_***_
61dee2a219f268bb2e91ba8f71b0f536_***_
d547bad707e12f5a9f12d4fcbeea87ed_***_Alex Lord
948a547e27d969b7e192b4620688704d_***_Steve Wilks
author


Alex Lord
Steve Wilks
author2
Jon E. Evans
Alex Lord
Nathan A. Smith
Michael B. Ward
Steve Wilks
format Journal article
container_title The Journal of Physical Chemistry C
container_volume 122
container_issue 43
container_start_page 24716
publishDate 2018
institution Swansea University
issn 1932-7447
1932-7455
doi_str_mv 10.1021/acs.jpcc.8b06757
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Engineering and Applied Sciences - Uncategorised{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Engineering and Applied Sciences - Uncategorised
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description Near-term commercialization of nanowire-based devices is possible through an integrative approach with existing semiconductor platforms. Research-based single nanowire devices suffer from issues related to size dependence and variability; hence, the use of a large number of nanowires in parallel is a prerequisite for real-world devices to scale output and provide statistical averaging of properties. Parallel integration is most directly achieved through electrical contacting of nanowire arrays in the as-grown vertical configuration. Here, we demonstrate a one-step process that overcomes several technological barriers simultaneously, allowing the seamless electrical integration of ZnO nanowire arrays with industry standard silicon substrates. Our seamless integration process is based on the deposition of a metal contact layer on silicon and subsequent CVD nanowire growth. Combined SEM, XRD, and TEM measurements show compositional and structural changes to each metal contact layer candidate during the high-temperature growth process, directly influencing the ZnO base growth and controlling the properties and dimensions of the resulting nanowire arrays. Findings were correlated to nanoscale multiprobe electrical measurements of individual nanowires in the vertical device configuration to demonstrate the effects of each metal layer on conduction through the nanowires and the metal–semiconductor interface. The refractory metal molybdenum gave highly aligned, dense nanowire growth and formed a low-resistance ohmic contact to the base of these arrays offering a simple and scalable process-ready solution for integrating nanowires with the industry standard silicon platform.
published_date 2018-12-31T04:36:29Z
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