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Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

Olujide A. Adenekan, Paul Holland, Karol Kalna Orcid Logo

Microelectronics Reliability, Volume: 99, Pages: 213 - 221

Swansea University Authors: Paul Holland, Karol Kalna Orcid Logo

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DOI (Published version): 10.1016/j.microrel.2019.04.008

Abstract

The scaling of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 50 V) requires a subsequent optimisation of SJ unit. The scaling and the SJ optimisation are carried out with physically based commercial TCAD device simulations by Silvaco. T...

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Published in: Microelectronics Reliability
ISSN: 0026-2714
Published: 2019
Online Access: Check full text

URI: https://cronfa.swan.ac.uk/Record/cronfa50951
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Abstract: The scaling of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 50 V) requires a subsequent optimisation of SJ unit. The scaling and the SJ optimisation are carried out with physically based commercial TCAD device simulations by Silvaco. The study is based on a meticulous calibration of drift-diffusion simulations against experimental characteristics of a 1 μm gate length SJ multi-gate MOSFET (SJ-MGFET) aiming at improving density, switching speed, drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate scaling of the device architecture to improve the device performance by optimising doping profile to achieve an avalanche-enabled device under a charge balanced condition. The optimised SJ-MGFETs scaled by a factor of 0.5 and 0.25, with a folded alternating U-shaped n/p-SJ drift region pillar of a width of 0.3 μm and a trench depth of 2.7 μm, achieve a low specific on-resistance (Ron,sp) of 7.68 mΩ⋅mm2 and 2.24 mΩ⋅mm2 (VGS = 10 V) and BV of 48 V and 26 V, respectively. The scaled 0.5 μm and 0.25 μm gate length SJ-MGFETs offer a transconductance (gm) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V, respectively, greatly improving the levels of integration in a CMOS architecture.
College: Faculty of Science and Engineering
Start Page: 213
End Page: 221

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