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Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications / Olujide A. Adenekan; Paul Holland; Karol Kalna

Microelectronics Reliability, Volume: 99, Pages: 213 - 221

Swansea University Authors: Paul, Holland, Karol, Kalna

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Abstract

The scaling of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 50 V) requires a subsequent optimisation of SJ unit. The scaling and the SJ optimisation are carried out with physically based commercial TCAD device simulations by Silvaco. T...

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Published in: Microelectronics Reliability
ISSN: 0026-2714
Published: 2019
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URI: https://cronfa.swan.ac.uk/Record/cronfa50951
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fullrecord <?xml version="1.0"?><rfc1807><datestamp>2019-07-02T15:53:41.3833609</datestamp><bib-version>v2</bib-version><id>50951</id><entry>2019-06-27</entry><title>Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub&#x2013;50&#x202F;V applications</title><swanseaauthors><author><sid>9c7eea4ea9d615fcbf2801a672dd2e7f</sid><firstname>Paul</firstname><surname>Holland</surname><name>Paul Holland</name><active>true</active><ethesisStudent>false</ethesisStudent></author><author><sid>1329a42020e44fdd13de2f20d5143253</sid><ORCID>0000-0002-6333-9189</ORCID><firstname>Karol</firstname><surname>Kalna</surname><name>Karol Kalna</name><active>true</active><ethesisStudent>false</ethesisStudent></author></swanseaauthors><date>2019-06-27</date><deptcode>EEN</deptcode><abstract>The scaling of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 50&#x202F;V) requires a subsequent optimisation of SJ unit. The scaling and the SJ optimisation are carried out with physically based commercial TCAD device simulations by Silvaco. The study is based on a meticulous calibration of drift-diffusion simulations against experimental characteristics of a 1&#x202F;&#x3BC;m gate length SJ multi-gate MOSFET (SJ-MGFET) aiming at improving density, switching speed, drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate scaling of the device architecture to improve the device performance by optimising doping profile to achieve an avalanche-enabled device under a charge balanced condition. The optimised SJ-MGFETs scaled by a factor of 0.5 and 0.25, with a folded alternating U-shaped n/p-SJ drift region pillar of a width of 0.3&#x202F;&#x3BC;m and a trench depth of 2.7&#x202F;&#x3BC;m, achieve a low specific on-resistance (Ron,sp) of 7.68&#x202F;m&#x3A9;&#x22C5;mm2 and 2.24&#x202F;m&#x3A9;&#x22C5;mm2 (VGS&#x202F;=&#x202F;10&#x202F;V) and BV of 48&#x202F;V and 26&#x202F;V, respectively. The scaled 0.5 &#x3BC;m and 0.25 &#x3BC;m gate length SJ-MGFETs offer a transconductance (gm) of 20&#x202F;mS/mm and 56&#x202F;mS/mm at a drain voltage of 0.1&#x202F;V, respectively, greatly improving the levels of integration in a CMOS architecture.</abstract><type>Journal Article</type><journal>Microelectronics Reliability</journal><volume>99</volume><paginationStart>213</paginationStart><paginationEnd>221</paginationEnd><publisher/><issnPrint>0026-2714</issnPrint><keywords/><publishedDay>31</publishedDay><publishedMonth>12</publishedMonth><publishedYear>2019</publishedYear><publishedDate>2019-12-31</publishedDate><doi>10.1016/j.microrel.2019.04.008</doi><url/><notes/><college>COLLEGE NANME</college><department>Engineering</department><CollegeCode>COLLEGE CODE</CollegeCode><DepartmentCode>EEN</DepartmentCode><institution>Swansea University</institution><apcterm/><lastEdited>2019-07-02T15:53:41.3833609</lastEdited><Created>2019-06-27T15:52:25.2956738</Created><path><level id="1">College of Engineering</level><level id="2">Engineering</level></path><authors><author><firstname>Olujide A.</firstname><surname>Adenekan</surname><order>1</order></author><author><firstname>Paul</firstname><surname>Holland</surname><order>2</order></author><author><firstname>Karol</firstname><surname>Kalna</surname><orcid>0000-0002-6333-9189</orcid><order>3</order></author></authors><documents><document><filename>0050951-02072019155245.pdf</filename><originalFilename>adenekan2019v2.pdf</originalFilename><uploaded>2019-07-02T15:52:45.6030000</uploaded><type>Output</type><contentLength>1565957</contentLength><contentType>application/pdf</contentType><version>Accepted Manuscript</version><cronfaStatus>true</cronfaStatus><action/><embargoDate>2020-06-21T00:00:00.0000000</embargoDate><documentNotes>&#xA9; 2019. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/</documentNotes><copyrightCorrect>false</copyrightCorrect><language>eng</language></document></documents><OutputDurs/></rfc1807>
spelling 2019-07-02T15:53:41.3833609 v2 50951 2019-06-27 Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications 9c7eea4ea9d615fcbf2801a672dd2e7f Paul Holland Paul Holland true false 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2019-06-27 EEN The scaling of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 50 V) requires a subsequent optimisation of SJ unit. The scaling and the SJ optimisation are carried out with physically based commercial TCAD device simulations by Silvaco. The study is based on a meticulous calibration of drift-diffusion simulations against experimental characteristics of a 1 μm gate length SJ multi-gate MOSFET (SJ-MGFET) aiming at improving density, switching speed, drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate scaling of the device architecture to improve the device performance by optimising doping profile to achieve an avalanche-enabled device under a charge balanced condition. The optimised SJ-MGFETs scaled by a factor of 0.5 and 0.25, with a folded alternating U-shaped n/p-SJ drift region pillar of a width of 0.3 μm and a trench depth of 2.7 μm, achieve a low specific on-resistance (Ron,sp) of 7.68 mΩ⋅mm2 and 2.24 mΩ⋅mm2 (VGS = 10 V) and BV of 48 V and 26 V, respectively. The scaled 0.5 μm and 0.25 μm gate length SJ-MGFETs offer a transconductance (gm) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V, respectively, greatly improving the levels of integration in a CMOS architecture. Journal Article Microelectronics Reliability 99 213 221 0026-2714 31 12 2019 2019-12-31 10.1016/j.microrel.2019.04.008 COLLEGE NANME Engineering COLLEGE CODE EEN Swansea University 2019-07-02T15:53:41.3833609 2019-06-27T15:52:25.2956738 College of Engineering Engineering Olujide A. Adenekan 1 Paul Holland 2 Karol Kalna 0000-0002-6333-9189 3 0050951-02072019155245.pdf adenekan2019v2.pdf 2019-07-02T15:52:45.6030000 Output 1565957 application/pdf Accepted Manuscript true 2020-06-21T00:00:00.0000000 © 2019. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/ false eng
title Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications
spellingShingle Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications
Paul, Holland
Karol, Kalna
title_short Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications
title_full Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications
title_fullStr Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications
title_full_unstemmed Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications
title_sort Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications
author_id_str_mv 9c7eea4ea9d615fcbf2801a672dd2e7f
1329a42020e44fdd13de2f20d5143253
author_id_fullname_str_mv 9c7eea4ea9d615fcbf2801a672dd2e7f_***_Paul, Holland
1329a42020e44fdd13de2f20d5143253_***_Karol, Kalna
author Paul, Holland
Karol, Kalna
author2 Olujide A. Adenekan
Paul Holland
Karol Kalna
format Journal article
container_title Microelectronics Reliability
container_volume 99
container_start_page 213
publishDate 2019
institution Swansea University
issn 0026-2714
doi_str_mv 10.1016/j.microrel.2019.04.008
college_str College of Engineering
hierarchytype
hierarchy_top_id collegeofengineering
hierarchy_top_title College of Engineering
hierarchy_parent_id collegeofengineering
hierarchy_parent_title College of Engineering
department_str Engineering{{{_:::_}}}College of Engineering{{{_:::_}}}Engineering
document_store_str 1
active_str 0
description The scaling of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 50 V) requires a subsequent optimisation of SJ unit. The scaling and the SJ optimisation are carried out with physically based commercial TCAD device simulations by Silvaco. The study is based on a meticulous calibration of drift-diffusion simulations against experimental characteristics of a 1 μm gate length SJ multi-gate MOSFET (SJ-MGFET) aiming at improving density, switching speed, drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate scaling of the device architecture to improve the device performance by optimising doping profile to achieve an avalanche-enabled device under a charge balanced condition. The optimised SJ-MGFETs scaled by a factor of 0.5 and 0.25, with a folded alternating U-shaped n/p-SJ drift region pillar of a width of 0.3 μm and a trench depth of 2.7 μm, achieve a low specific on-resistance (Ron,sp) of 7.68 mΩ⋅mm2 and 2.24 mΩ⋅mm2 (VGS = 10 V) and BV of 48 V and 26 V, respectively. The scaled 0.5 μm and 0.25 μm gate length SJ-MGFETs offer a transconductance (gm) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V, respectively, greatly improving the levels of integration in a CMOS architecture.
published_date 2019-12-31T04:06:53Z
_version_ 1706858605400031232
score 10.809259