No Cover Image

Conference contribution 389 views

A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture / P.M Holland; M. P Elwin; S Batcup; Z Zhou; P. M Igic

Microelectronics, 2008. MIEL 2008. 26th International Conference on, Pages: 177 - 179

Swansea University Author: Holland, Paul

Full text not available from this repository: check for access using links below.

DOI (Published version): 10.1109/ICMEL.2008.4559252

Published in: Microelectronics, 2008. MIEL 2008. 26th International Conference on
Published: 2008
URI: https://cronfa.swan.ac.uk/Record/cronfa5751
Tags: Add Tag
No Tags, Be the first to tag this record!
Item Description: A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture.This paper presents a novel approach to implement a high voltage transistor into a CMOS process and study the effects on circuit reliability.
College: College of Engineering
Start Page: 177
End Page: 179