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LDMOSFET with drain potential suppression for 100V Power IC technology / Paul, Holland
Microelectronics Reliability, Volume: 51, Issue: 3, Pages: 529 - 535
Swansea University Author: Paul, Holland
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LDMOSFET with drain potential suppression for 100V Power IC technology
|Published in:||Microelectronics Reliability|
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A £1M WAG KEF grant to Swansea generated many high impact papers subitted to RAE.These activities and publications triggered world-wide interest and Diodes ZETEX, one of the world’s largest semiconductor manufacturers and its engineers tested Swansea’s designed silicon chips and verified the findings. The cooperation with Diodes ZETEX and X-Fab led to an £1M Power System on Chip Development DTI grant (2006 - 2009). The industrial part of the DTI funded research was led by Prof Glenn Birchby, Chief Scientist at Diodes, and Dr Brendan Bold, Process Development Director, X-Fab Semiconductor Foundries. After the completion, the grant has been marked excellent by the TSB and achieved 95% of its targets. This paper reports on the outputs of the project. The LDMOS transistors designed by Swansea reduced the On-Resistance by more than half compared to X-Fab's previous design. They also extended the breakdwon voltage to more than 100V allowing modern LED lighting control designs to be introduced into CMOS. The papers reports how Dr Holland et al successfully transferred technology to a silicon foundry and is being used for high voltgae Power IC designs.
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