E-Thesis 699 views 367 downloads
Development of Silicon Carbide Devices for Next-Generation Surge Protection and Power Electronics / FINNIAN MONAGHAN
Swansea University Author: FINNIAN MONAGHAN
DOI (Published version): 10.23889/SUThesis.70068
Abstract
Silicon Carbide (SiC) power devices are becoming popular in a variety of different applications, however one un-tapped sector for SiC is the circuit protection market. Specifically depletion-mode SiC JFETs could be utilised in over-current/voltage protection products such as Bourns’ Transient Blockin...
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Swansea University, Wales, UK
2025
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| Institution: | Swansea University |
| Degree level: | Doctoral |
| Degree name: | EngD |
| Supervisor: | Jennings, M. R., and Martinez, A. E. |
| URI: | https://cronfa.swan.ac.uk/Record/cronfa70068 |
| Abstract: |
Silicon Carbide (SiC) power devices are becoming popular in a variety of different applications, however one un-tapped sector for SiC is the circuit protection market. Specifically depletion-mode SiC JFETs could be utilised in over-current/voltage protection products such as Bourns’ Transient Blocking Unit (TBU®) product line to enhance efficiency, and penetrate previously unfeasible high voltage markets. This thesis investigates and begins the development of 4H-SiC JFETs specifically de-signed for the TBU® application. Extensive optimisation of the JFET cell and termination design are explored using finite-element simulations. The trade-off between JFET off-state performance and design parameters is identified. For the first time, Short Channel Effects (SCEs) are comprehensively shown to affect JFET behaviour when the channel length is short. In particular, JFET breakdown voltage can be degraded to only 50V for a 1200V drift region if channel length is short. It is demonstrated that by introducing sidewall P-type implants, the JFET channel can be extended without requiring high implantation energies, and completely eliminates the premature device failure caused by SCEs. This is demonstrated to improve breakdown voltage by 1000V in some cases. A new 4H-SiC JFET design integrating a temperature sensor on the semiconductor surface is also demonstrated using finite-element simulations. The sensor consists of a lateral P-type resistor formed simultaneously with the P+ gate junction. Electrothermal simulationswere employed to consider device self-heating effects showed the sensor had an R2 of 0.996,which is comparable to other 4H-SiC temperature sensors. The sensor was also shown to be stable under high drain bias when blocking, with Isens only varying by 4% between Vd= 0V and 1000V. Process optimization was also completed on three key elements of the JFET fabrication process: carbon capping layers used for surface protection, P-type implant activation, and P-type ohmic contacts. The P+ gate junction is a fundamental part of the JFET unit cell structure. It was found that Tanneal= 1700°C resulted in the highest percentage of implanted dopants becoming electrically, with 26.9% activation. Furthermore, it was also found that ohmic contacts using the Ti/Al/Ni metal scheme offered the lowest specific contact resistivity of 4.91 106Ωcm2, which was achieved after annealing at 1050°C for 2 minutes. |
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| Keywords: |
Silicon Carbide, Power Electronics, JFET, TCAD, ohmic contact |
| College: |
Faculty of Science and Engineering |
| Funders: |
Coated M2A CDT, Bourns. Inc |