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Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes

N Seoane, M Aldegunde, D Nagy, M A Elmessary, G Indalecio, A J García-Loureiro, K Kalna, Karol Kalna Orcid Logo

Semiconductor Science and Technology, Volume: 31, Issue: 7, Start page: 075005

Swansea University Author: Karol Kalna Orcid Logo

DOI (Published version): 10.1088/0268-1242/31/7/075005

Abstract

We investigate the performance and scalability of III-V-OI In0.53Ga0.47As and SOI Si FinFETs using state-of-the-art in-house-built 3D simulation tools. Three different technology nodes specified in the ITRS have been analysed with gate lengths (L G) of 14.0 nm, 12.8 and 10.4 nm for the InGaAs FinFET...

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Published in: Semiconductor Science and Technology
Published: 2016
URI: https://cronfa.swan.ac.uk/Record/cronfa29411
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Abstract: We investigate the performance and scalability of III-V-OI In0.53Ga0.47As and SOI Si FinFETs using state-of-the-art in-house-built 3D simulation tools. Three different technology nodes specified in the ITRS have been analysed with gate lengths (L G) of 14.0 nm, 12.8 and 10.4 nm for the InGaAs FinFETs and 12.8 nm, 10.7 and 8.1 nm for the Si devices. At a high drain bias, the 12.8 and 10.4 nm InGaAs FinFETs deliver 15% and 13% larger on-currents but 14% larger off-currents than the equivalent 12.8 and 10.7 nm Si FinFETs, respectively. For equivalent gate lengths, both the InGaAs and the Si FinFETs have the same I ON/I OFF ratio (5.9 × 104 when L G = 12.8 nm and 5.7 × 104 when L G = 10.4(10.7) nm). A more pronounced S/D tunnelling affecting the InGaAs FinFETs leads to a larger deterioration in their SS (less than 10%) and DIBL (around 20%) compared to the Si counterparts.
College: College of Engineering
Issue: 7
Start Page: 075005