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Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

Daniel Nagy, Gabriel Espineira, Guillermo Indalecio, Antonio J. Garcia-Loureiro, Karol Kalna Orcid Logo, Natalia Seoane

IEEE Access, Volume: 8, Pages: 53196 - 53202

Swansea University Author: Karol Kalna Orcid Logo

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DOI (Published version): 10.1109/access.2020.2980925

Abstract

Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length ( LG ) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based...

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Published in: IEEE Access
ISSN: 2169-3536
Published: Institute of Electrical and Electronics Engineers (IEEE) 2020
Online Access: Check full text

URI: https://cronfa.swan.ac.uk/Record/cronfa53939
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Abstract: Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length ( LG ) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to LG of 16 nm offering a larger on-current ( ION ) and slightly better sub-threshold characteristics. Below LG of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current ( IOFF ), and the largest ION/IOFF ratio out of the three architectures. However, the NW FET suffers from early ION saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body.
College: Professional Services
Funders: University of Santiago De Compostela
Start Page: 53196
End Page: 53202

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