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Scaling/LER Study of Si GAA Nanowire FET using 3D Finite Element Monte Carlo Simulations / Muhammad A. Elmessary, Daniel Nagy, Manuel Aldegunde, Natalia Seoane, Guillermo Indalecio, Jari Lindberg, Wulf Dettmer, Djordje Perić, Antonio J. García-Loureiro, Karol Kalna, Djordje Peric

Solid-State Electronics, Volume: 128, Pages: 17 - 24

Swansea University Authors: Wulf Dettmer, Karol Kalna, Djordje Peric

Abstract

3D Finite Element (FE) Monte Carlo (MC) simulation toolbox incorporating 2D Schrödinger equation quantum corrections is employed to simulate ID-VG characteristics of a 22 nm gate length gate-all-around (GAA) Si nanowire (NW) FET demonstrating an excellent agreement against experimental data at both...

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Published in: Solid-State Electronics
ISSN: 0038-1101
Published: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) 2017
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URI: https://cronfa.swan.ac.uk/Record/cronfa30748
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spelling 2019-07-02T14:35:12.8158803 v2 30748 2016-10-21 Scaling/LER Study of Si GAA Nanowire FET using 3D Finite Element Monte Carlo Simulations 30bb53ad906e7160e947fa01c16abf55 0000-0003-0799-4645 Wulf Dettmer Wulf Dettmer true false 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 9d35cb799b2542ad39140943a9a9da65 0000-0002-1112-301X Djordje Peric Djordje Peric true false 2016-10-21 AERO 3D Finite Element (FE) Monte Carlo (MC) simulation toolbox incorporating 2D Schrödinger equation quantum corrections is employed to simulate ID-VG characteristics of a 22 nm gate length gate-all-around (GAA) Si nanowire (NW) FET demonstrating an excellent agreement against experimental data at both low and high drain biases. We then scale the Si GAA NW according to the ITRS specifications to a gate length of 10 nm predicting that the NW FET will deliver the required on-current of above 1mA/μm and a superior electrostatic integrity with a nearly ideal sub-threshold slope of 68 mV/dec and a DIBL of 39 mV/V. In addition, we use a calibrated 3D FE quantum corrected drift-diffusion (DD) toolbox to investigate the effects of NW line-edge roughness (LER) induced variability on the sub-threshold characteristics (threshold voltage (VT), OFF-current (IOFF), sub-threshold slope (SS) and drain-induced-barrier-lowering (DIBL)) for the 22 nm and 10 nm gate length GAA NW FETs at low and high drain biases. We simulate variability with two LER correlation lengths (CL=20 nm and 10 nm) and three root mean square values (RMS=0.6,0.7 and 0.85 nm). Journal Article Solid-State Electronics 128 17 24 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) 0038-1101 28 2 2017 2017-02-28 10.1016/j.sse.2016.10.018 COLLEGE NANME Aerospace Engineering COLLEGE CODE AERO Swansea University 2019-07-02T14:35:12.8158803 2016-10-21T09:48:21.0239041 College of Engineering Engineering Muhammad A. Elmessary 1 Daniel Nagy 2 Manuel Aldegunde 3 Natalia Seoane 4 Guillermo Indalecio 5 Jari Lindberg 6 Wulf Dettmer 0000-0003-0799-4645 7 Djordje Perić 8 Antonio J. García-Loureiro 9 Karol Kalna 0000-0002-6333-9189 10 Djordje Peric 0000-0002-1112-301X 11 0030748-21102016094937.pdf elmessary2016(2).pdf 2016-10-21T09:49:37.7000000 Output 2505630 application/pdf Accepted Manuscript true 2017-10-18T00:00:00.0000000 false
title Scaling/LER Study of Si GAA Nanowire FET using 3D Finite Element Monte Carlo Simulations
spellingShingle Scaling/LER Study of Si GAA Nanowire FET using 3D Finite Element Monte Carlo Simulations
Wulf, Dettmer
Karol, Kalna
Djordje, Peric
title_short Scaling/LER Study of Si GAA Nanowire FET using 3D Finite Element Monte Carlo Simulations
title_full Scaling/LER Study of Si GAA Nanowire FET using 3D Finite Element Monte Carlo Simulations
title_fullStr Scaling/LER Study of Si GAA Nanowire FET using 3D Finite Element Monte Carlo Simulations
title_full_unstemmed Scaling/LER Study of Si GAA Nanowire FET using 3D Finite Element Monte Carlo Simulations
title_sort Scaling/LER Study of Si GAA Nanowire FET using 3D Finite Element Monte Carlo Simulations
author_id_str_mv 30bb53ad906e7160e947fa01c16abf55
1329a42020e44fdd13de2f20d5143253
9d35cb799b2542ad39140943a9a9da65
author_id_fullname_str_mv 30bb53ad906e7160e947fa01c16abf55_***_Wulf, Dettmer
1329a42020e44fdd13de2f20d5143253_***_Karol, Kalna
9d35cb799b2542ad39140943a9a9da65_***_Djordje, Peric
author Wulf, Dettmer
Karol, Kalna
Djordje, Peric
author2 Muhammad A. Elmessary
Daniel Nagy
Manuel Aldegunde
Natalia Seoane
Guillermo Indalecio
Jari Lindberg
Wulf Dettmer
Djordje Perić
Antonio J. García-Loureiro
Karol Kalna
Djordje Peric
format Journal article
container_title Solid-State Electronics
container_volume 128
container_start_page 17
publishDate 2017
institution Swansea University
issn 0038-1101
doi_str_mv 10.1016/j.sse.2016.10.018
publisher 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
college_str College of Engineering
hierarchytype
hierarchy_top_id collegeofengineering
hierarchy_top_title College of Engineering
hierarchy_parent_id collegeofengineering
hierarchy_parent_title College of Engineering
department_str Engineering{{{_:::_}}}College of Engineering{{{_:::_}}}Engineering
document_store_str 1
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description 3D Finite Element (FE) Monte Carlo (MC) simulation toolbox incorporating 2D Schrödinger equation quantum corrections is employed to simulate ID-VG characteristics of a 22 nm gate length gate-all-around (GAA) Si nanowire (NW) FET demonstrating an excellent agreement against experimental data at both low and high drain biases. We then scale the Si GAA NW according to the ITRS specifications to a gate length of 10 nm predicting that the NW FET will deliver the required on-current of above 1mA/μm and a superior electrostatic integrity with a nearly ideal sub-threshold slope of 68 mV/dec and a DIBL of 39 mV/V. In addition, we use a calibrated 3D FE quantum corrected drift-diffusion (DD) toolbox to investigate the effects of NW line-edge roughness (LER) induced variability on the sub-threshold characteristics (threshold voltage (VT), OFF-current (IOFF), sub-threshold slope (SS) and drain-induced-barrier-lowering (DIBL)) for the 22 nm and 10 nm gate length GAA NW FETs at low and high drain biases. We simulate variability with two LER correlation lengths (CL=20 nm and 10 nm) and three root mean square values (RMS=0.6,0.7 and 0.85 nm).
published_date 2017-02-28T03:43:52Z
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