Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology

Benbakhti, Brahim; Chan, Kah Hou; Soltani, Ali; Kalna, Karol

doi:10.1109/TED.2016.2603188

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Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology

Brahim Benbakhti, Kah Hou Chan, Ali Soltani, Karol Kalna

IEEE Transactions on Electron Devices, Volume: 63, Issue: 10, Pages: 3893 - 3899

Swansea University Author: Karol Kalna

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DOI (Published version): 10.1109/TED.2016.2603188

Abstract

The device and circuit performance of InGaAs and Ge hybrid CMOS with a gate length of 20 nm using an implant free quantum well (QW) device architecture is evaluated using a multi-scale methodology by ensemble Monte Carlo simulation, drift-diffusion simulation, compact modeling, and TCAD mixed-mode c...

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Published in:	IEEE Transactions on Electron Devices
ISSN:	0018-9383 1557-9646
Published:	2016
Online Access:	Check full text
URI:	https://cronfa.swan.ac.uk/Record/cronfa33255
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first_indexed	2017-05-08T19:00:30Z
last_indexed	2018-09-26T18:36:54Z
id	cronfa33255
recordtype	SURis
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spelling	2018-09-26T16:57:17.2193816 v2 33255 2017-05-08 Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2017-05-08 EEEG The device and circuit performance of InGaAs and Ge hybrid CMOS with a gate length of 20 nm using an implant free quantum well (QW) device architecture is evaluated using a multi-scale methodology by ensemble Monte Carlo simulation, drift-diffusion simulation, compact modeling, and TCAD mixed-mode circuit simulation. We report that the QW and doped substrate of the hybrid CMOS help to reduce short channel effects (SCE) by enhanced carrier confinement. The QW architecture reduces the negative impact of a low density of states in III-V materials. In addition, the calculated access resistance is found to be a much lower than in Si counterparts thanks to a heavily doped overgrowth source/drain contact. We predict an overall low gate capacitance and a large drive current when compared with Si-CMOS that leads to a significant reduction in a circuit propagation time delay (5.5 ps). Journal Article IEEE Transactions on Electron Devices 63 10 3893 3899 0018-9383 1557-9646 TCAD, III–V, CMOS, compact modeling, drift diffusion (DD), Ge, Monte Carlo (MC) 31 10 2016 2016-10-31 10.1109/TED.2016.2603188 http://ieeexplore.ieee.org/document/7563860/ TED on III-V/Ge CMOS: Have been used in the development of new emerging nano-CMOS technology (Meuris Marc meuris@imec.be, program manager at IMEC)add TSMC, IBM, and GlobalFoundries COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University RCUK 2018-09-26T16:57:17.2193816 2017-05-08T18:47:57.5252022 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Brahim Benbakhti 1 Kah Hou Chan 2 Ali Soltani 3 Karol Kalna 0000-0002-6333-9189 4
title	Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology
spellingShingle	Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology Karol Kalna
title_short	Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology
title_full	Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology
title_fullStr	Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology
title_full_unstemmed	Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology
title_sort	Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology
author_id_str_mv	1329a42020e44fdd13de2f20d5143253
author_id_fullname_str_mv	1329a42020e44fdd13de2f20d5143253_***_Karol Kalna
author	Karol Kalna
author2	Brahim Benbakhti Kah Hou Chan Ali Soltani Karol Kalna
format	Journal article
container_title	IEEE Transactions on Electron Devices
container_volume	63
container_issue	10
container_start_page	3893
publishDate	2016
institution	Swansea University
issn	0018-9383 1557-9646
doi_str_mv	10.1109/TED.2016.2603188
college_str	Faculty of Science and Engineering
hierarchytype
hierarchy_top_id	facultyofscienceandengineering
hierarchy_top_title	Faculty of Science and Engineering
hierarchy_parent_id	facultyofscienceandengineering
hierarchy_parent_title	Faculty of Science and Engineering
department_str	School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
url	http://ieeexplore.ieee.org/document/7563860/
document_store_str	0
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description	The device and circuit performance of InGaAs and Ge hybrid CMOS with a gate length of 20 nm using an implant free quantum well (QW) device architecture is evaluated using a multi-scale methodology by ensemble Monte Carlo simulation, drift-diffusion simulation, compact modeling, and TCAD mixed-mode circuit simulation. We report that the QW and doped substrate of the hybrid CMOS help to reduce short channel effects (SCE) by enhanced carrier confinement. The QW architecture reduces the negative impact of a low density of states in III-V materials. In addition, the calculated access resistance is found to be a much lower than in Si counterparts thanks to a heavily doped overgrowth source/drain contact. We predict an overall low gate capacitance and a large drive current when compared with Si-CMOS that leads to a significant reduction in a circuit propagation time delay (5.5 ps).
published_date	2016-10-31T03:40:55Z
_version_	1763751866326319104
score	11.016235

Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology

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