Journal article 1268 views
Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures
Karol Kalna 
Microelectronics Reliability
Swansea University Author:
Karol Kalna
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DOI (Published version): 10.1016/j.microrel.2009.11.017
Abstract
Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures
| Published in: | Microelectronics Reliability |
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| Published: |
2010
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| URI: | https://cronfa.swan.ac.uk/Record/cronfa6065 |
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| College: |
Faculty of Science and Engineering |
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