No Cover Image

Journal article 983 views

Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures

Karol Kalna Orcid Logo

Microelectronics Reliability

Swansea University Author: Karol Kalna Orcid Logo

Full text not available from this repository: check for access using links below.

DOI (Published version): 10.1016/j.microrel.2009.11.017

Published in: Microelectronics Reliability
Published: 2010
Tags: Add Tag
No Tags, Be the first to tag this record!
College: Faculty of Science and Engineering