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Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures

Karol Kalna Orcid Logo

Microelectronics Reliability

Swansea University Author: Karol Kalna Orcid Logo

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DOI (Published version): 10.1016/j.microrel.2009.11.017

Published in: Microelectronics Reliability
Published: 2010
URI: https://cronfa.swan.ac.uk/Record/cronfa6065
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College: College of Engineering