Journal article 1268 views
Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures
Microelectronics Reliability
Swansea University Author: Karol Kalna
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DOI (Published version): 10.1016/j.microrel.2009.11.017
Abstract
Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures
Published in: | Microelectronics Reliability |
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Published: |
2010
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URI: | https://cronfa.swan.ac.uk/Record/cronfa6065 |
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2011-10-01T00:00:00.0000000 v2 6065 2013-09-03 Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2013-09-03 EEEG Journal Article Microelectronics Reliability 31 12 2010 2010-12-31 10.1016/j.microrel.2009.11.017 COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University 2011-10-01T00:00:00.0000000 2013-09-03T06:35:55.0000000 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Karol Kalna 0000-0002-6333-9189 1 |
title |
Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures |
spellingShingle |
Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures Karol Kalna |
title_short |
Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures |
title_full |
Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures |
title_fullStr |
Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures |
title_full_unstemmed |
Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures |
title_sort |
Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures |
author_id_str_mv |
1329a42020e44fdd13de2f20d5143253 |
author_id_fullname_str_mv |
1329a42020e44fdd13de2f20d5143253_***_Karol Kalna |
author |
Karol Kalna |
author2 |
Karol Kalna |
format |
Journal article |
container_title |
Microelectronics Reliability |
publishDate |
2010 |
institution |
Swansea University |
doi_str_mv |
10.1016/j.microrel.2009.11.017 |
college_str |
Faculty of Science and Engineering |
hierarchytype |
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facultyofscienceandengineering |
hierarchy_top_title |
Faculty of Science and Engineering |
hierarchy_parent_id |
facultyofscienceandengineering |
hierarchy_parent_title |
Faculty of Science and Engineering |
department_str |
School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering |
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published_date |
2010-12-31T03:07:27Z |
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1763749760543490048 |
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11.035349 |