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Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET / Karol, Kalna

IEEE Electron Device Letters, Volume: 40, Issue: 4, Pages: 510 - 513

Swansea University Author: Karol, Kalna

Abstract

The effect of gate edge roughness (GER) in the sub-threshold region is studied for two state-of-the-art architectures: a 10.7-nm Si FinFET and a 10-nm Si gateall-around (GAA) nanowire (NW) FET using an in-house 3D quantum-corrected drift-diffusion simulation tool. The GER is applied to the device ga...

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Published in: IEEE Electron Device Letters
ISSN: 0741-3106 1558-0563
Published: 2019
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URI: https://cronfa.swan.ac.uk/Record/cronfa50182
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spelling 2019-05-27T15:05:34.6413574 v2 50182 2019-05-01 Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2019-05-01 EEN The effect of gate edge roughness (GER) in the sub-threshold region is studied for two state-of-the-art architectures: a 10.7-nm Si FinFET and a 10-nm Si gateall-around (GAA) nanowire (NW) FET using an in-house 3D quantum-corrected drift-diffusion simulation tool. The GER is applied to the device gate using the characteristic values of root-mean-square amplitude and correlation length (CL). The GER-induced variability results in a standard deviation (σ) for the threshold voltage (V T ) of 7 mV for the FinFET when CL/Gate Perimeter = 0.66 and RMS = 0.80 nm, which is 20% greater than that of the GAA NW FET. GER is a less damaging source of variability than metal grain granularity (MGG), line edge roughness (LER), and random dopants (RD) for both devices. When compared to LER variations, σV T due to the GER is 62% and 86% lower for the FinFET and GAA NW FET, respectively. However, although GER affects the FinFET more than the GAA NW FET, the combined variability effect of GER, MGG, LER, and RD (σV T,comb ) on the FinFET is 30 mV, a value approximately 50% smaller than that of the GAA NW FET. Journal Article IEEE Electron Device Letters 40 4 510 513 0741-3106 1558-0563 31 12 2019 2019-12-31 10.1109/LED.2019.2900494 COLLEGE NANME Engineering COLLEGE CODE EEN Swansea University 2019-05-27T15:05:34.6413574 2019-05-01T10:21:50.1385920 College of Engineering Engineering G. Espineira 1 D. Nagy 2 G. Indalecio 3 A. J. Garcia-Loureiro 4 K. Kalna 5 N. Seoane 6 Karol Kalna 0000-0002-6333-9189 7 0050182-07052019085337.pdf espineira2019.pdf 2019-05-07T08:53:37.1130000 Output 10354958 application/pdf Accepted Manuscript true 2019-05-07T00:00:00.0000000 true eng
title Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET
spellingShingle Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET
Karol, Kalna
title_short Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET
title_full Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET
title_fullStr Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET
title_full_unstemmed Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET
title_sort Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET
author_id_str_mv 1329a42020e44fdd13de2f20d5143253
author_id_fullname_str_mv 1329a42020e44fdd13de2f20d5143253_***_Karol, Kalna
author Karol, Kalna
format Journal article
container_title IEEE Electron Device Letters
container_volume 40
container_issue 4
container_start_page 510
publishDate 2019
institution Swansea University
issn 0741-3106
1558-0563
doi_str_mv 10.1109/LED.2019.2900494
college_str College of Engineering
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hierarchy_top_title College of Engineering
hierarchy_parent_id collegeofengineering
hierarchy_parent_title College of Engineering
department_str Engineering{{{_:::_}}}College of Engineering{{{_:::_}}}Engineering
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description The effect of gate edge roughness (GER) in the sub-threshold region is studied for two state-of-the-art architectures: a 10.7-nm Si FinFET and a 10-nm Si gateall-around (GAA) nanowire (NW) FET using an in-house 3D quantum-corrected drift-diffusion simulation tool. The GER is applied to the device gate using the characteristic values of root-mean-square amplitude and correlation length (CL). The GER-induced variability results in a standard deviation (σ) for the threshold voltage (V T ) of 7 mV for the FinFET when CL/Gate Perimeter = 0.66 and RMS = 0.80 nm, which is 20% greater than that of the GAA NW FET. GER is a less damaging source of variability than metal grain granularity (MGG), line edge roughness (LER), and random dopants (RD) for both devices. When compared to LER variations, σV T due to the GER is 62% and 86% lower for the FinFET and GAA NW FET, respectively. However, although GER affects the FinFET more than the GAA NW FET, the combined variability effect of GER, MGG, LER, and RD (σV T,comb ) on the FinFET is 30 mV, a value approximately 50% smaller than that of the GAA NW FET.
published_date 2019-12-31T04:17:14Z
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