No Cover Image

Journal article 559 views

Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs / K Kalna, N Seoane, A.J Garcia-Loureiro, I.G Thayne, A Asenov, Karol Kalna

IEEE Transactions on Electron Devices, Volume: 55, Issue: 9, Pages: 2297 - 2306

Swansea University Author: Karol Kalna

Full text not available from this repository: check for access using links below.

Published in: IEEE Transactions on Electron Devices
ISSN: 0018-9383
Published: 2008
Online Access: Check full text

URI: https://cronfa.swan.ac.uk/Record/cronfa6074
Tags: Add Tag
No Tags, Be the first to tag this record!
first_indexed 2013-07-23T11:56:08Z
last_indexed 2018-02-09T04:33:13Z
id cronfa6074
recordtype SURis
fullrecord <?xml version="1.0"?><rfc1807><datestamp>2015-05-30T21:09:42.5914393</datestamp><bib-version>v2</bib-version><id>6074</id><entry>2013-09-03</entry><title>Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs</title><swanseaauthors><author><sid>1329a42020e44fdd13de2f20d5143253</sid><ORCID>0000-0002-6333-9189</ORCID><firstname>Karol</firstname><surname>Kalna</surname><name>Karol Kalna</name><active>true</active><ethesisStudent>false</ethesisStudent></author></swanseaauthors><date>2013-09-03</date><deptcode>EEEG</deptcode><abstract></abstract><type>Journal Article</type><journal>IEEE Transactions on Electron Devices</journal><volume>55</volume><journalNumber>9</journalNumber><paginationStart>2297</paginationStart><paginationEnd>2306</paginationEnd><publisher/><issnPrint>0018-9383</issnPrint><issnElectronic/><keywords/><publishedDay>31</publishedDay><publishedMonth>12</publishedMonth><publishedYear>2008</publishedYear><publishedDate>2008-12-31</publishedDate><doi>10.1109/TED.2008.927658</doi><url/><notes>A novel, n-type implant-free III-V MOSFETs with a high indium content (In0.75Ga0.25As) channel is studied using state-of-the-art finite-element heterostructure Monte Carlo and parallel 3-D drift-diffusion simulations. The device design is a result of 3-year No. 1 ranked STREP FP7 Project DUALLOGIC with 8 European Partners and two large EPSRC grants to develop III-V MOSFETs (Sub 100 nm III-V MOSFETs for Digital Applications and III-V MOSFETs for Ultimate CMOS ). III-V MOSFETs are currently intensively investigated for future digital application for the 15 or 11 nm CMOS technology with substantially funded R&amp;D (~$100M) by Intel, IBM, SEMATECH and SELETE.</notes><college>COLLEGE NANME</college><department>Electronic and Electrical Engineering</department><CollegeCode>COLLEGE CODE</CollegeCode><DepartmentCode>EEEG</DepartmentCode><institution>Swansea University</institution><apcterm/><lastEdited>2015-05-30T21:09:42.5914393</lastEdited><Created>2013-09-03T06:36:04.0000000</Created><path><level id="1">College of Engineering</level><level id="2">Engineering</level></path><authors><author><firstname>K</firstname><surname>Kalna</surname><order>1</order></author><author><firstname>N</firstname><surname>Seoane</surname><order>2</order></author><author><firstname>A.J</firstname><surname>Garcia-Loureiro</surname><order>3</order></author><author><firstname>I.G</firstname><surname>Thayne</surname><order>4</order></author><author><firstname>A</firstname><surname>Asenov</surname><order>5</order></author><author><firstname>Karol</firstname><surname>Kalna</surname><orcid>0000-0002-6333-9189</orcid><order>6</order></author></authors><documents/><OutputDurs/></rfc1807>
spelling 2015-05-30T21:09:42.5914393 v2 6074 2013-09-03 Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2013-09-03 EEEG Journal Article IEEE Transactions on Electron Devices 55 9 2297 2306 0018-9383 31 12 2008 2008-12-31 10.1109/TED.2008.927658 A novel, n-type implant-free III-V MOSFETs with a high indium content (In0.75Ga0.25As) channel is studied using state-of-the-art finite-element heterostructure Monte Carlo and parallel 3-D drift-diffusion simulations. The device design is a result of 3-year No. 1 ranked STREP FP7 Project DUALLOGIC with 8 European Partners and two large EPSRC grants to develop III-V MOSFETs (Sub 100 nm III-V MOSFETs for Digital Applications and III-V MOSFETs for Ultimate CMOS ). III-V MOSFETs are currently intensively investigated for future digital application for the 15 or 11 nm CMOS technology with substantially funded R&D (~$100M) by Intel, IBM, SEMATECH and SELETE. COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University 2015-05-30T21:09:42.5914393 2013-09-03T06:36:04.0000000 College of Engineering Engineering K Kalna 1 N Seoane 2 A.J Garcia-Loureiro 3 I.G Thayne 4 A Asenov 5 Karol Kalna 0000-0002-6333-9189 6
title Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs
spellingShingle Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs
Karol, Kalna
title_short Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs
title_full Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs
title_fullStr Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs
title_full_unstemmed Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs
title_sort Benchmarking of Scaled InGaAs Implant-Free NanoMOSFETs
author_id_str_mv 1329a42020e44fdd13de2f20d5143253
author_id_fullname_str_mv 1329a42020e44fdd13de2f20d5143253_***_Karol, Kalna
author Karol, Kalna
author2 K Kalna
N Seoane
A.J Garcia-Loureiro
I.G Thayne
A Asenov
Karol Kalna
format Journal article
container_title IEEE Transactions on Electron Devices
container_volume 55
container_issue 9
container_start_page 2297
publishDate 2008
institution Swansea University
issn 0018-9383
doi_str_mv 10.1109/TED.2008.927658
college_str College of Engineering
hierarchytype
hierarchy_top_id collegeofengineering
hierarchy_top_title College of Engineering
hierarchy_parent_id collegeofengineering
hierarchy_parent_title College of Engineering
department_str Engineering{{{_:::_}}}College of Engineering{{{_:::_}}}Engineering
document_store_str 0
active_str 0
published_date 2008-12-31T03:18:12Z
_version_ 1714646881926119424
score 10.83191