No Cover Image

Journal article 613 views 300 downloads

A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind

Roland Mumford Orcid Logo, Janet Hopkins Orcid Logo, Owen Guy Orcid Logo

IEEE Transactions on Semiconductor Manufacturing, Volume: 36, Issue: 2, Pages: 188 - 196

Swansea University Author: Owen Guy Orcid Logo

Check full text

DOI (Published version): 10.1109/tsm.2023.3255939

Abstract

3D wafer packaging represents a significant component of the total wafer level processing cost. Replacement of the Chemical Mechanical Polishing (CMP) process step with a corresponding dry etch can yield significant time and cost savings. Incorporating equipment already utilized in the 3D integrated...

Full description

Published in: IEEE Transactions on Semiconductor Manufacturing
ISSN: 0894-6507 1558-2345
Published: Institute of Electrical and Electronics Engineers (IEEE) 2023
Online Access: Check full text

URI: https://cronfa.swan.ac.uk/Record/cronfa63131
Tags: Add Tag
No Tags, Be the first to tag this record!
first_indexed 2023-04-12T12:53:57Z
last_indexed 2023-04-14T03:23:53Z
id cronfa63131
recordtype SURis
fullrecord <?xml version="1.0" encoding="utf-8"?><rfc1807 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema"><bib-version>v2</bib-version><id>63131</id><entry>2023-04-12</entry><title>A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind</title><swanseaauthors><author><sid>c7fa5949b8528e048c5b978005f66794</sid><ORCID>0000-0002-6449-4033</ORCID><firstname>Owen</firstname><surname>Guy</surname><name>Owen Guy</name><active>true</active><ethesisStudent>false</ethesisStudent></author></swanseaauthors><date>2023-04-12</date><deptcode>CHEM</deptcode><abstract>3D wafer packaging represents a significant component of the total wafer level processing cost. Replacement of the Chemical Mechanical Polishing (CMP) process step with a corresponding dry etch can yield significant time and cost savings. Incorporating equipment already utilized in the 3D integrated wafer packaging process during the subsequent Through Silicon Via (TSV) reveal step, process efficiencies can be achieved, with overall die yields being maintained. Using dry etch technology to treat a 200nm rough back-ground silicon surface, a smooth surface with a peak to valley roughness of less than 6nm is demonstrated. This patented process differs from other dry etch smoothing techniques in that it aims to eliminate any visual grind marks rather than just reducing the surface roughness. The elimination of visible grind marks is critical in later optical inspection where they are falsely identified as defects. The quality of the surface is equivalent to that of a CMP processed wafer and as such, this process has been implemented in manufacturing replacing the CMP step. The novel process described combines a surface modification followed by a roughness reduction in an iterative manner to produce a smooth surface without visible grind marks post processing.</abstract><type>Journal Article</type><journal>IEEE Transactions on Semiconductor Manufacturing</journal><volume>36</volume><journalNumber>2</journalNumber><paginationStart>188</paginationStart><paginationEnd>196</paginationEnd><publisher>Institute of Electrical and Electronics Engineers (IEEE)</publisher><placeOfPublication/><isbnPrint/><isbnElectronic/><issnPrint>0894-6507</issnPrint><issnElectronic>1558-2345</issnElectronic><keywords/><publishedDay>1</publishedDay><publishedMonth>5</publishedMonth><publishedYear>2023</publishedYear><publishedDate>2023-05-01</publishedDate><doi>10.1109/tsm.2023.3255939</doi><url>http://dx.doi.org/10.1109/tsm.2023.3255939</url><notes/><college>COLLEGE NANME</college><department>Chemistry</department><CollegeCode>COLLEGE CODE</CollegeCode><DepartmentCode>CHEM</DepartmentCode><institution>Swansea University</institution><apcterm/><funders/><projectreference/><lastEdited>2023-05-19T15:53:52.7156212</lastEdited><Created>2023-04-12T13:49:59.2709959</Created><path><level id="1">Faculty of Science and Engineering</level><level id="2">School of Engineering and Applied Sciences - Chemistry</level></path><authors><author><firstname>Roland</firstname><surname>Mumford</surname><orcid>0000-0002-5081-1851</orcid><order>1</order></author><author><firstname>Janet</firstname><surname>Hopkins</surname><orcid>0009-0006-1627-9650</orcid><order>2</order></author><author><firstname>Owen</firstname><surname>Guy</surname><orcid>0000-0002-6449-4033</orcid><order>3</order></author></authors><documents><document><filename>63131__27030__6689dc4d75884224a35639666100a72c.pdf</filename><originalFilename>63131.pdf</originalFilename><uploaded>2023-04-13T11:54:04.5204749</uploaded><type>Output</type><contentLength>1391782</contentLength><contentType>application/pdf</contentType><version>Accepted Manuscript</version><cronfaStatus>true</cronfaStatus><copyrightCorrect>false</copyrightCorrect><language>eng</language></document></documents><OutputDurs/></rfc1807>
spelling v2 63131 2023-04-12 A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind c7fa5949b8528e048c5b978005f66794 0000-0002-6449-4033 Owen Guy Owen Guy true false 2023-04-12 CHEM 3D wafer packaging represents a significant component of the total wafer level processing cost. Replacement of the Chemical Mechanical Polishing (CMP) process step with a corresponding dry etch can yield significant time and cost savings. Incorporating equipment already utilized in the 3D integrated wafer packaging process during the subsequent Through Silicon Via (TSV) reveal step, process efficiencies can be achieved, with overall die yields being maintained. Using dry etch technology to treat a 200nm rough back-ground silicon surface, a smooth surface with a peak to valley roughness of less than 6nm is demonstrated. This patented process differs from other dry etch smoothing techniques in that it aims to eliminate any visual grind marks rather than just reducing the surface roughness. The elimination of visible grind marks is critical in later optical inspection where they are falsely identified as defects. The quality of the surface is equivalent to that of a CMP processed wafer and as such, this process has been implemented in manufacturing replacing the CMP step. The novel process described combines a surface modification followed by a roughness reduction in an iterative manner to produce a smooth surface without visible grind marks post processing. Journal Article IEEE Transactions on Semiconductor Manufacturing 36 2 188 196 Institute of Electrical and Electronics Engineers (IEEE) 0894-6507 1558-2345 1 5 2023 2023-05-01 10.1109/tsm.2023.3255939 http://dx.doi.org/10.1109/tsm.2023.3255939 COLLEGE NANME Chemistry COLLEGE CODE CHEM Swansea University 2023-05-19T15:53:52.7156212 2023-04-12T13:49:59.2709959 Faculty of Science and Engineering School of Engineering and Applied Sciences - Chemistry Roland Mumford 0000-0002-5081-1851 1 Janet Hopkins 0009-0006-1627-9650 2 Owen Guy 0000-0002-6449-4033 3 63131__27030__6689dc4d75884224a35639666100a72c.pdf 63131.pdf 2023-04-13T11:54:04.5204749 Output 1391782 application/pdf Accepted Manuscript true false eng
title A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind
spellingShingle A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind
Owen Guy
title_short A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind
title_full A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind
title_fullStr A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind
title_full_unstemmed A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind
title_sort A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind
author_id_str_mv c7fa5949b8528e048c5b978005f66794
author_id_fullname_str_mv c7fa5949b8528e048c5b978005f66794_***_Owen Guy
author Owen Guy
author2 Roland Mumford
Janet Hopkins
Owen Guy
format Journal article
container_title IEEE Transactions on Semiconductor Manufacturing
container_volume 36
container_issue 2
container_start_page 188
publishDate 2023
institution Swansea University
issn 0894-6507
1558-2345
doi_str_mv 10.1109/tsm.2023.3255939
publisher Institute of Electrical and Electronics Engineers (IEEE)
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Engineering and Applied Sciences - Chemistry{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Engineering and Applied Sciences - Chemistry
url http://dx.doi.org/10.1109/tsm.2023.3255939
document_store_str 1
active_str 0
description 3D wafer packaging represents a significant component of the total wafer level processing cost. Replacement of the Chemical Mechanical Polishing (CMP) process step with a corresponding dry etch can yield significant time and cost savings. Incorporating equipment already utilized in the 3D integrated wafer packaging process during the subsequent Through Silicon Via (TSV) reveal step, process efficiencies can be achieved, with overall die yields being maintained. Using dry etch technology to treat a 200nm rough back-ground silicon surface, a smooth surface with a peak to valley roughness of less than 6nm is demonstrated. This patented process differs from other dry etch smoothing techniques in that it aims to eliminate any visual grind marks rather than just reducing the surface roughness. The elimination of visible grind marks is critical in later optical inspection where they are falsely identified as defects. The quality of the surface is equivalent to that of a CMP processed wafer and as such, this process has been implemented in manufacturing replacing the CMP step. The novel process described combines a surface modification followed by a roughness reduction in an iterative manner to produce a smooth surface without visible grind marks post processing.
published_date 2023-05-01T15:53:51Z
_version_ 1766334693133778944
score 11.03034

Similar Items