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GaAs Growth on Ge‐Buffered Discontinuous (111)‐Faceted V‐Groove Silicon Substrates

Makhayeni Mtunzi Orcid Logo, Hui Jia Orcid Logo, Mateus G. Masteghin Orcid Logo, Yaonan Hou Orcid Logo, Haotian Zeng Orcid Logo, Huiwen Deng, Jae‐Seong Park, Chong Chen, Jun Li, Xingzhao Yan Orcid Logo, Ilias Skandalos Orcid Logo, Frederic Gardes, Mingchu Tang, Alwyn Seeds Orcid Logo, Huiyun Liu Orcid Logo

Advanced Physics Research, Volume: 4, Issue: 9, Start page: 2500026

Swansea University Author: Yaonan Hou Orcid Logo

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DOI (Published version): 10.1002/apxr.202500026

Abstract

The propagation of antiphase boundaries (APBs) and threading dislocations (TDs) poses a significant impediment to the realisation of high‐quality group III–V semiconductors grown on group IV platforms. The complete annihilation of APBs and a substantial reduction in threading dislocation density (TD...

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Published in: Advanced Physics Research
ISSN: 2751-1200
Published: Wiley 2025
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URI: https://cronfa.swan.ac.uk/Record/cronfa69543
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fullrecord <?xml version="1.0"?><rfc1807><datestamp>2025-11-10T14:37:59.8311347</datestamp><bib-version>v2</bib-version><id>69543</id><entry>2025-05-20</entry><title>GaAs Growth on Ge&#x2010;Buffered Discontinuous (111)&#x2010;Faceted V&#x2010;Groove Silicon Substrates</title><swanseaauthors><author><sid>113975f710084997abdb26ad5fa03e8e</sid><ORCID>0000-0001-9461-3841</ORCID><firstname>Yaonan</firstname><surname>Hou</surname><name>Yaonan Hou</name><active>true</active><ethesisStudent>false</ethesisStudent></author></swanseaauthors><date>2025-05-20</date><deptcode>ACEM</deptcode><abstract>The propagation of antiphase boundaries (APBs) and threading dislocations (TDs) poses a significant impediment to the realisation of high&#x2010;quality group III&#x2013;V semiconductors grown on group IV platforms. The complete annihilation of APBs and a substantial reduction in threading dislocation density (TDD) are essential for achieving high&#x2010;efficiency III&#x2013;V devices compatible with complementary metal&#x2010;oxide semiconductor (CMOS) technology. In this study, a novel growth technique is proposed and developed to fabricate a faceted germanium (Ge) buffer on a discontinuous (111)&#x2010;faceted V&#x2010;groove silicon (Si) substrate with a 500 nm flat ridge width. Subsequently, a GaAs buffer is grown on the Ge/V&#x2010;groove Si virtual substrate using a ramped temperature growth process to minimise the prevalence of line and planar defects in the buffer structure. An APB&#x2010;free GaAs buffer is successfully achieved, as confirmed by cross&#x2010;sectional and plan&#x2010;view transmission electron microscopy (TEM) and atomic force microscopy (AFM) analyses. The faceted Ge buffer layer obtained through this innovative approach alleviates the stringent fabrication requirements and intricate processing typically associated with conventional continuous V&#x2010;groove Si substrates. This advancement facilitates the development of photonic integrated circuits by providing a simplified and efficient alternative substrate solution.</abstract><type>Journal Article</type><journal>Advanced Physics Research</journal><volume>4</volume><journalNumber>9</journalNumber><paginationStart>2500026</paginationStart><paginationEnd/><publisher>Wiley</publisher><placeOfPublication/><isbnPrint/><isbnElectronic/><issnPrint/><issnElectronic>2751-1200</issnElectronic><keywords>antiphase boundaries, aspect ratio trapping, threading dislocations, v-groove</keywords><publishedDay>1</publishedDay><publishedMonth>9</publishedMonth><publishedYear>2025</publishedYear><publishedDate>2025-09-01</publishedDate><doi>10.1002/apxr.202500026</doi><url/><notes/><college>COLLEGE NANME</college><department>Aerospace, Civil, Electrical, and Mechanical Engineering</department><CollegeCode>COLLEGE CODE</CollegeCode><DepartmentCode>ACEM</DepartmentCode><institution>Swansea University</institution><apcterm>Another institution paid the OA fee</apcterm><funders>This work was supported by the UK Engineering and Physical Sciences Research Council (EP/Z532848/1, EP/X015300/1, EP/T028475/1, EP/S024441/1, and EP/P006973/1).</funders><projectreference/><lastEdited>2025-11-10T14:37:59.8311347</lastEdited><Created>2025-05-20T14:29:15.8235555</Created><path><level id="1">Faculty of Science and Engineering</level><level id="2">School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering</level></path><authors><author><firstname>Makhayeni</firstname><surname>Mtunzi</surname><orcid>0009-0000-3924-2726</orcid><order>1</order></author><author><firstname>Hui</firstname><surname>Jia</surname><orcid>0000-0002-8325-3948</orcid><order>2</order></author><author><firstname>Mateus G.</firstname><surname>Masteghin</surname><orcid>0000-0002-5672-8311</orcid><order>3</order></author><author><firstname>Yaonan</firstname><surname>Hou</surname><orcid>0000-0001-9461-3841</orcid><order>4</order></author><author><firstname>Haotian</firstname><surname>Zeng</surname><orcid>0000-0002-7328-9576</orcid><order>5</order></author><author><firstname>Huiwen</firstname><surname>Deng</surname><order>6</order></author><author><firstname>Jae&#x2010;Seong</firstname><surname>Park</surname><order>7</order></author><author><firstname>Chong</firstname><surname>Chen</surname><order>8</order></author><author><firstname>Jun</firstname><surname>Li</surname><order>9</order></author><author><firstname>Xingzhao</firstname><surname>Yan</surname><orcid>0000-0002-2466-3015</orcid><order>10</order></author><author><firstname>Ilias</firstname><surname>Skandalos</surname><orcid>0000-0002-9021-1420</orcid><order>11</order></author><author><firstname>Frederic</firstname><surname>Gardes</surname><order>12</order></author><author><firstname>Mingchu</firstname><surname>Tang</surname><order>13</order></author><author><firstname>Alwyn</firstname><surname>Seeds</surname><orcid>0000-0002-5228-627X</orcid><order>14</order></author><author><firstname>Huiyun</firstname><surname>Liu</surname><orcid>0000-0002-7654-8553</orcid><order>15</order></author></authors><documents><document><filename>69543__34320__aaec7fc079494148b1d5fa147827fecf.pdf</filename><originalFilename>apxr.202500026.pdf</originalFilename><uploaded>2025-05-20T14:29:15.8201473</uploaded><type>Output</type><contentLength>2395288</contentLength><contentType>application/pdf</contentType><version>Version of Record</version><cronfaStatus>true</cronfaStatus><documentNotes>&#xA9; 2025 The Author(s). This is an open access article under the terms of the Creative Commons Attribution License (CC BY).</documentNotes><copyrightCorrect>true</copyrightCorrect><language>eng</language><licence>http://creativecommons.org/licenses/by/4.0/</licence></document></documents><OutputDurs/></rfc1807>
spelling 2025-11-10T14:37:59.8311347 v2 69543 2025-05-20 GaAs Growth on Ge‐Buffered Discontinuous (111)‐Faceted V‐Groove Silicon Substrates 113975f710084997abdb26ad5fa03e8e 0000-0001-9461-3841 Yaonan Hou Yaonan Hou true false 2025-05-20 ACEM The propagation of antiphase boundaries (APBs) and threading dislocations (TDs) poses a significant impediment to the realisation of high‐quality group III–V semiconductors grown on group IV platforms. The complete annihilation of APBs and a substantial reduction in threading dislocation density (TDD) are essential for achieving high‐efficiency III–V devices compatible with complementary metal‐oxide semiconductor (CMOS) technology. In this study, a novel growth technique is proposed and developed to fabricate a faceted germanium (Ge) buffer on a discontinuous (111)‐faceted V‐groove silicon (Si) substrate with a 500 nm flat ridge width. Subsequently, a GaAs buffer is grown on the Ge/V‐groove Si virtual substrate using a ramped temperature growth process to minimise the prevalence of line and planar defects in the buffer structure. An APB‐free GaAs buffer is successfully achieved, as confirmed by cross‐sectional and plan‐view transmission electron microscopy (TEM) and atomic force microscopy (AFM) analyses. The faceted Ge buffer layer obtained through this innovative approach alleviates the stringent fabrication requirements and intricate processing typically associated with conventional continuous V‐groove Si substrates. This advancement facilitates the development of photonic integrated circuits by providing a simplified and efficient alternative substrate solution. Journal Article Advanced Physics Research 4 9 2500026 Wiley 2751-1200 antiphase boundaries, aspect ratio trapping, threading dislocations, v-groove 1 9 2025 2025-09-01 10.1002/apxr.202500026 COLLEGE NANME Aerospace, Civil, Electrical, and Mechanical Engineering COLLEGE CODE ACEM Swansea University Another institution paid the OA fee This work was supported by the UK Engineering and Physical Sciences Research Council (EP/Z532848/1, EP/X015300/1, EP/T028475/1, EP/S024441/1, and EP/P006973/1). 2025-11-10T14:37:59.8311347 2025-05-20T14:29:15.8235555 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Makhayeni Mtunzi 0009-0000-3924-2726 1 Hui Jia 0000-0002-8325-3948 2 Mateus G. Masteghin 0000-0002-5672-8311 3 Yaonan Hou 0000-0001-9461-3841 4 Haotian Zeng 0000-0002-7328-9576 5 Huiwen Deng 6 Jae‐Seong Park 7 Chong Chen 8 Jun Li 9 Xingzhao Yan 0000-0002-2466-3015 10 Ilias Skandalos 0000-0002-9021-1420 11 Frederic Gardes 12 Mingchu Tang 13 Alwyn Seeds 0000-0002-5228-627X 14 Huiyun Liu 0000-0002-7654-8553 15 69543__34320__aaec7fc079494148b1d5fa147827fecf.pdf apxr.202500026.pdf 2025-05-20T14:29:15.8201473 Output 2395288 application/pdf Version of Record true © 2025 The Author(s). This is an open access article under the terms of the Creative Commons Attribution License (CC BY). true eng http://creativecommons.org/licenses/by/4.0/
title GaAs Growth on Ge‐Buffered Discontinuous (111)‐Faceted V‐Groove Silicon Substrates
spellingShingle GaAs Growth on Ge‐Buffered Discontinuous (111)‐Faceted V‐Groove Silicon Substrates
Yaonan Hou
title_short GaAs Growth on Ge‐Buffered Discontinuous (111)‐Faceted V‐Groove Silicon Substrates
title_full GaAs Growth on Ge‐Buffered Discontinuous (111)‐Faceted V‐Groove Silicon Substrates
title_fullStr GaAs Growth on Ge‐Buffered Discontinuous (111)‐Faceted V‐Groove Silicon Substrates
title_full_unstemmed GaAs Growth on Ge‐Buffered Discontinuous (111)‐Faceted V‐Groove Silicon Substrates
title_sort GaAs Growth on Ge‐Buffered Discontinuous (111)‐Faceted V‐Groove Silicon Substrates
author_id_str_mv 113975f710084997abdb26ad5fa03e8e
author_id_fullname_str_mv 113975f710084997abdb26ad5fa03e8e_***_Yaonan Hou
author Yaonan Hou
author2 Makhayeni Mtunzi
Hui Jia
Mateus G. Masteghin
Yaonan Hou
Haotian Zeng
Huiwen Deng
Jae‐Seong Park
Chong Chen
Jun Li
Xingzhao Yan
Ilias Skandalos
Frederic Gardes
Mingchu Tang
Alwyn Seeds
Huiyun Liu
format Journal article
container_title Advanced Physics Research
container_volume 4
container_issue 9
container_start_page 2500026
publishDate 2025
institution Swansea University
issn 2751-1200
doi_str_mv 10.1002/apxr.202500026
publisher Wiley
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
document_store_str 1
active_str 0
description The propagation of antiphase boundaries (APBs) and threading dislocations (TDs) poses a significant impediment to the realisation of high‐quality group III–V semiconductors grown on group IV platforms. The complete annihilation of APBs and a substantial reduction in threading dislocation density (TDD) are essential for achieving high‐efficiency III–V devices compatible with complementary metal‐oxide semiconductor (CMOS) technology. In this study, a novel growth technique is proposed and developed to fabricate a faceted germanium (Ge) buffer on a discontinuous (111)‐faceted V‐groove silicon (Si) substrate with a 500 nm flat ridge width. Subsequently, a GaAs buffer is grown on the Ge/V‐groove Si virtual substrate using a ramped temperature growth process to minimise the prevalence of line and planar defects in the buffer structure. An APB‐free GaAs buffer is successfully achieved, as confirmed by cross‐sectional and plan‐view transmission electron microscopy (TEM) and atomic force microscopy (AFM) analyses. The faceted Ge buffer layer obtained through this innovative approach alleviates the stringent fabrication requirements and intricate processing typically associated with conventional continuous V‐groove Si substrates. This advancement facilitates the development of photonic integrated circuits by providing a simplified and efficient alternative substrate solution.
published_date 2025-09-01T05:28:54Z
_version_ 1856805519322251264
score 11.09611

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