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NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants

A Martinez, M Aldegunde, A.R Brown, S Roy, A Asenov, Antonio Martinez Muniz Orcid Logo

Solid-State Electronics, Volume: 71, Pages: 101 - 105

Swansea University Author: Antonio Martinez Muniz Orcid Logo

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Published in: Solid-State Electronics
ISSN: 0038-1101
Published: 2012
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URI: https://cronfa.swan.ac.uk/Record/cronfa10579
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first_indexed 2013-07-23T12:06:48Z
last_indexed 2018-02-09T04:39:29Z
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fullrecord <?xml version="1.0"?><rfc1807><datestamp>2016-08-17T13:50:53.7253244</datestamp><bib-version>v2</bib-version><id>10579</id><entry>2013-09-03</entry><title>NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants</title><swanseaauthors><author><sid>cd433784251add853672979313f838ec</sid><ORCID>0000-0001-8131-7242</ORCID><firstname>Antonio</firstname><surname>Martinez Muniz</surname><name>Antonio Martinez Muniz</name><active>true</active><ethesisStudent>false</ethesisStudent></author></swanseaauthors><date>2013-09-03</date><deptcode>EEEG</deptcode><abstract></abstract><type>Journal Article</type><journal>Solid-State Electronics</journal><volume>71</volume><paginationStart>101</paginationStart><paginationEnd>105</paginationEnd><publisher/><issnPrint>0038-1101</issnPrint><keywords/><publishedDay>31</publishedDay><publishedMonth>12</publishedMonth><publishedYear>2012</publishedYear><publishedDate>2012-12-31</publishedDate><doi>10.1016/j.sse.2011.10.028</doi><url/><notes>This paper first appeared at the ULIS (Ireland) conference and was subsequently invited for publication in Solid state electronics journal, as it showed that extremely scaled junctionless transistors with channel lengths smaller than 20 nm and 5x5 nm2 cross section have large variability due to random dopant fluctuations. These junctionless devices appear as an attractive alternative to conventional junction MOSFET transistors in future device miniaturisation.</notes><college>COLLEGE NANME</college><department>Electronic and Electrical Engineering</department><CollegeCode>COLLEGE CODE</CollegeCode><DepartmentCode>EEEG</DepartmentCode><institution>Swansea University</institution><apcterm/><lastEdited>2016-08-17T13:50:53.7253244</lastEdited><Created>2013-09-03T06:39:05.0000000</Created><path><level id="1">College of Engineering</level><level id="2">Engineering</level></path><authors><author><firstname>A</firstname><surname>Martinez</surname><order>1</order></author><author><firstname>M</firstname><surname>Aldegunde</surname><order>2</order></author><author><firstname>A.R</firstname><surname>Brown</surname><order>3</order></author><author><firstname>S</firstname><surname>Roy</surname><order>4</order></author><author><firstname>A</firstname><surname>Asenov</surname><order>5</order></author><author><firstname>Antonio</firstname><surname>Martinez Muniz</surname><orcid>0000-0001-8131-7242</orcid><order>6</order></author></authors><documents/><OutputDurs/></rfc1807>
spelling 2016-08-17T13:50:53.7253244 v2 10579 2013-09-03 NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants cd433784251add853672979313f838ec 0000-0001-8131-7242 Antonio Martinez Muniz Antonio Martinez Muniz true false 2013-09-03 EEEG Journal Article Solid-State Electronics 71 101 105 0038-1101 31 12 2012 2012-12-31 10.1016/j.sse.2011.10.028 This paper first appeared at the ULIS (Ireland) conference and was subsequently invited for publication in Solid state electronics journal, as it showed that extremely scaled junctionless transistors with channel lengths smaller than 20 nm and 5x5 nm2 cross section have large variability due to random dopant fluctuations. These junctionless devices appear as an attractive alternative to conventional junction MOSFET transistors in future device miniaturisation. COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University 2016-08-17T13:50:53.7253244 2013-09-03T06:39:05.0000000 College of Engineering Engineering A Martinez 1 M Aldegunde 2 A.R Brown 3 S Roy 4 A Asenov 5 Antonio Martinez Muniz 0000-0001-8131-7242 6
title NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants
spellingShingle NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants
Antonio Martinez Muniz
title_short NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants
title_full NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants
title_fullStr NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants
title_full_unstemmed NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants
title_sort NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants
author_id_str_mv cd433784251add853672979313f838ec
author_id_fullname_str_mv cd433784251add853672979313f838ec_***_Antonio Martinez Muniz
author Antonio Martinez Muniz
author2 A Martinez
M Aldegunde
A.R Brown
S Roy
A Asenov
Antonio Martinez Muniz
format Journal article
container_title Solid-State Electronics
container_volume 71
container_start_page 101
publishDate 2012
institution Swansea University
issn 0038-1101
doi_str_mv 10.1016/j.sse.2011.10.028
college_str College of Engineering
hierarchytype
hierarchy_top_id collegeofengineering
hierarchy_top_title College of Engineering
hierarchy_parent_id collegeofengineering
hierarchy_parent_title College of Engineering
department_str Engineering{{{_:::_}}}College of Engineering{{{_:::_}}}Engineering
document_store_str 0
active_str 0
published_date 2012-12-31T03:20:06Z
_version_ 1737024451630858240
score 10.900759