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3-D Finite Element Monte Carlo Simulations of Scaled Si SOI FinFET With Different Cross Sections / Daniel Nagy, Muhammad A. Elmessary, Manuel Aldegunde, Raul Valin, Antonio Martinez, Jari Lindberg, Wulf Dettmer, Djordje Peric, Antonio J. Garcia-Loureiro, Karol Kalna, Antonio Martinez Muniz

IEEE Transactions on Nanotechnology, Volume: 14, Issue: 1, Pages: 93 - 100

Swansea University Authors: Wulf Dettmer, Djordje Peric, Karol Kalna, Antonio Martinez Muniz

Abstract

Si SOI FinFETs with gate lengths of 12.8 nm and 10.7 nm are modelled using 3D Finite Element Monte Carlo (MC) simulations with 2D Schroedinger equation quantum corrections. These non-planar transistors are studied for two cross-sections: rectangular-like and triangular-like, and for two channel orie...

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Published in: IEEE Transactions on Nanotechnology
ISSN: 1941-0085
Published: 2015
Online Access: Check full text

URI: https://cronfa.swan.ac.uk/Record/cronfa21854
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Abstract: Si SOI FinFETs with gate lengths of 12.8 nm and 10.7 nm are modelled using 3D Finite Element Monte Carlo (MC) simulations with 2D Schroedinger equation quantum corrections. These non-planar transistors are studied for two cross-sections: rectangular-like and triangular-like, and for two channel orientations: h100i and h110i. The 10.7 nm gate length rectangular-like FinFET is also simulated using the 3D Non-Equilibrium Green’s Functions (NEGF) technique and the results are compared with MC simulations. The 12.8 nm and 10.7 nm gate length rectangular-like FinFETs give larger drive currents per perimeter by about 25−27% than the triangular-like shaped but are outperformed by the triangular-like ones when normalised by channel area. The devices with a <100> channel orientation deliver a larger drive current by about 11% than their counterparts with a h110i channel when scaled to 12.8 nm and to 10.7 nm gate lengths. ID–VG characteristics at low and high drain biases obtained from the 3D NEGF simulations show a remarkable agreement with the MC results and overestimate the drain current from a gate bias of 0.5 V only due to exclusion of the interface roughness and ionized impurity scatterings.
Item Description: This work is licensed under a Creative Commons Attribution 3.0 License. For more information, see http://creativecommons.org/licenses/by/3.0/
College: College of Engineering
Issue: 1
Start Page: 93
End Page: 100