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Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications
Semiconductor Science and Technology, Volume: 36, Issue: 5, Start page: 055006
Swansea University Author: Mike Jennings
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This letter reports on initial investigation results on the material quality and device suitability of a homo-epitaxial 3C-SiC growth process. Atomic force microscopy surface investigations revealed root-mean square surface roughness levels of 163.21 nm, which was shown to be caused by pits (35 μm w...
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This letter reports on initial investigation results on the material quality and device suitability of a homo-epitaxial 3C-SiC growth process. Atomic force microscopy surface investigations revealed root-mean square surface roughness levels of 163.21 nm, which was shown to be caused by pits (35 μm width and 450 nm depth) with a density of 1.09 × 105 cm−2 which had formed during material growth. On wider scan areas, the formation of these were seen to be caused by step bunching, revealing the need for further epitaxial process improvement. X-ray diffraction showed good average crystalline qualities with a full width of half-maximum of 160 arcseconds for the 3C-SiC (002) being lower than for the 3C-on-Si material (210 arcseconds). The analysis of C–V curves then revealed similar interface-trapped charge levels for freestanding 3C-SiC, 3C-SiC on Si and 4H-SiC, with forming gas post-deposition annealed freestanding 3C-SiC devices showing DIT levels of 3.3 × 1011 cm−2 eV−1 at EC−ET = 0.2 eV. The homo-epitaxially grown 3C-SiC material's suitability for MOS applications could also be confirmed by leakage current measurements.
3C-SiC, homo-epitaxial growth, CVD, AFM, XRD, MOSCAP, DIT, leakage
Faculty of Science and Engineering
EPSRC project EP/P017363/1 and the CHALLENGE project (HORIZON 2020-NMBP-720827). The CHALLENGE project is a research and innovation action funded by the European Union's Horizon 2020 program.