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Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications

A B Renz, F Li, O J Vavasour, P M Gammon, T Dai, G W C Baker, F La Via, M Zielinski, L Zhang, N E Grant, J D Murphy, P A Mawby, Mike Jennings Orcid Logo, V A Shah

Semiconductor Science and Technology, Volume: 36, Issue: 5, Start page: 055006

Swansea University Author: Mike Jennings Orcid Logo

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Abstract

This letter reports on initial investigation results on the material quality and device suitability of a homo-epitaxial 3C-SiC growth process. Atomic force microscopy surface investigations revealed root-mean square surface roughness levels of 163.21 nm, which was shown to be caused by pits (35 μm w...

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Published in: Semiconductor Science and Technology
ISSN: 0268-1242 1361-6641
Published: IOP Publishing 2021
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URI: https://cronfa.swan.ac.uk/Record/cronfa56858
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spelling 2021-05-26T12:33:13.6101805 v2 56858 2021-05-13 Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications e0ba5d7ece08cd70c9f8f8683996454a 0000-0003-3270-0805 Mike Jennings Mike Jennings true false 2021-05-13 EEEG This letter reports on initial investigation results on the material quality and device suitability of a homo-epitaxial 3C-SiC growth process. Atomic force microscopy surface investigations revealed root-mean square surface roughness levels of 163.21 nm, which was shown to be caused by pits (35 μm width and 450 nm depth) with a density of 1.09 × 105 cm−2 which had formed during material growth. On wider scan areas, the formation of these were seen to be caused by step bunching, revealing the need for further epitaxial process improvement. X-ray diffraction showed good average crystalline qualities with a full width of half-maximum of 160 arcseconds for the 3C-SiC (002) being lower than for the 3C-on-Si material (210 arcseconds). The analysis of C–V curves then revealed similar interface-trapped charge levels for freestanding 3C-SiC, 3C-SiC on Si and 4H-SiC, with forming gas post-deposition annealed freestanding 3C-SiC devices showing DIT levels of 3.3 × 1011 cm−2 eV−1 at EC−ET = 0.2 eV. The homo-epitaxially grown 3C-SiC material's suitability for MOS applications could also be confirmed by leakage current measurements. Journal Article Semiconductor Science and Technology 36 5 055006 IOP Publishing 0268-1242 1361-6641 3C-SiC, homo-epitaxial growth, CVD, AFM, XRD, MOSCAP, DIT, leakage 1 5 2021 2021-05-01 10.1088/1361-6641/abefa1 COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University 2021-05-26T12:33:13.6101805 2021-05-13T09:48:26.6183109 College of Engineering Engineering A B Renz 1 F Li 2 O J Vavasour 3 P M Gammon 4 T Dai 5 G W C Baker 6 F La Via 7 M Zielinski 8 L Zhang 9 N E Grant 10 J D Murphy 11 P A Mawby 12 Mike Jennings 0000-0003-3270-0805 13 V A Shah 14 56858__19861__ca795044d88246cc9103ec5e3810b979.pdf 56858.pdf 2021-05-13T09:49:41.6933879 Output 1840936 application/pdf Version of Record true © 2021 The Author(s). Released under the terms of the Creative Commons Attribution 4.0 license true eng http://creativecommons.org/licenses/by/4.0/
title Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications
spellingShingle Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications
Mike, Jennings
title_short Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications
title_full Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications
title_fullStr Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications
title_full_unstemmed Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications
title_sort Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications
author_id_str_mv e0ba5d7ece08cd70c9f8f8683996454a
author_id_fullname_str_mv e0ba5d7ece08cd70c9f8f8683996454a_***_Mike, Jennings_***_0000-0003-3270-0805
author Mike, Jennings
author2 A B Renz
F Li
O J Vavasour
P M Gammon
T Dai
G W C Baker
F La Via
M Zielinski
L Zhang
N E Grant
J D Murphy
P A Mawby
Mike Jennings
V A Shah
format Journal article
container_title Semiconductor Science and Technology
container_volume 36
container_issue 5
container_start_page 055006
publishDate 2021
institution Swansea University
issn 0268-1242
1361-6641
doi_str_mv 10.1088/1361-6641/abefa1
publisher IOP Publishing
college_str College of Engineering
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hierarchy_top_id collegeofengineering
hierarchy_top_title College of Engineering
hierarchy_parent_id collegeofengineering
hierarchy_parent_title College of Engineering
department_str Engineering{{{_:::_}}}College of Engineering{{{_:::_}}}Engineering
document_store_str 1
active_str 0
description This letter reports on initial investigation results on the material quality and device suitability of a homo-epitaxial 3C-SiC growth process. Atomic force microscopy surface investigations revealed root-mean square surface roughness levels of 163.21 nm, which was shown to be caused by pits (35 μm width and 450 nm depth) with a density of 1.09 × 105 cm−2 which had formed during material growth. On wider scan areas, the formation of these were seen to be caused by step bunching, revealing the need for further epitaxial process improvement. X-ray diffraction showed good average crystalline qualities with a full width of half-maximum of 160 arcseconds for the 3C-SiC (002) being lower than for the 3C-on-Si material (210 arcseconds). The analysis of C–V curves then revealed similar interface-trapped charge levels for freestanding 3C-SiC, 3C-SiC on Si and 4H-SiC, with forming gas post-deposition annealed freestanding 3C-SiC devices showing DIT levels of 3.3 × 1011 cm−2 eV−1 at EC−ET = 0.2 eV. The homo-epitaxially grown 3C-SiC material's suitability for MOS applications could also be confirmed by leakage current measurements.
published_date 2021-05-01T04:24:05Z
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score 10.852379