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Scaling Challenges of Nanosheet Field-Effect Transistors Into Sub-2 nm Nodes

Murad Alabdullah, Muhammad Elmessary Orcid Logo, Daniel Nagy, N. Seoane Orcid Logo, A. J. García-Loureiro Orcid Logo, Karol Kalna Orcid Logo

IEEE Journal of the Electron Devices Society, Volume: 12, Pages: 479 - 485

Swansea University Authors: Murad Alabdullah, Muhammad Elmessary Orcid Logo, Daniel Nagy, Karol Kalna Orcid Logo

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DOI (Published version): 10.1109/jeds.2024.3416200

Abstract

The scaling of nanosheet (NS) field effect transistors (FETs) from the 12 nm gate length to the ultimate gate length of 10 nm for sub-2 nm nodes brings additional technological challenges. Here, 3D finite element Monte Carlo simulations are employed to explore how to alter the NS architecture to inc...

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Published in: IEEE Journal of the Electron Devices Society
ISSN: 2168-6734
Published: Institute of Electrical and Electronics Engineers (IEEE) 2024
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URI: https://cronfa.swan.ac.uk/Record/cronfa70729
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Here, 3D finite element Monte Carlo simulations are employed to explore how to alter the NS architecture to increase the drive current ( IDD ) because the gate scaling to 10 nm results in a decline of the current (by 10.7 %). IDD of the 10 nm gate length NS FET will increase by 11% if the maximum n-type source/drain doping reaches 1&#xD7;1020cm&#x2212;3 , or increase by 3.8 % if the high- &#x3BA; dielectric layer equivalent oxide thickness (EOT) is less than 1.0 nm. The reduction in the channel width below 40 nm or the reduction in the channel thickness below 5 nm will substantially decrease IDD. The sub-threshold figures of merit like the sub-threshold slope (SS) will decrease from 75 to 73 mV/dec, while the drain-induced barrier lowering (DIBL) will increase from 32 to 77 mV/V. Finally, the effect of strain to increase the drive current is strongly limited by quantum confinement. IDD will increase by 3% and by 14% in the 10 nm gate NS FET with the &#x27E8;110&#x27E9; and &#x27E8;100&#x27E9; channel orientations, respectively, when a strain of 0.5 % is applied to the channel, with a negligible increase for larger strain values ( 0.7 % and 1.0 %).</abstract><type>Journal Article</type><journal>IEEE Journal of the Electron Devices Society</journal><volume>12</volume><journalNumber/><paginationStart>479</paginationStart><paginationEnd>485</paginationEnd><publisher>Institute of Electrical and Electronics Engineers (IEEE)</publisher><placeOfPublication/><isbnPrint/><isbnElectronic/><issnPrint/><issnElectronic>2168-6734</issnElectronic><keywords/><publishedDay>18</publishedDay><publishedMonth>6</publishedMonth><publishedYear>2024</publishedYear><publishedDate>2024-06-18</publishedDate><doi>10.1109/jeds.2024.3416200</doi><url/><notes/><college>COLLEGE NANME</college><department>Mathematics and Computer Science School</department><CollegeCode>COLLEGE CODE</CollegeCode><DepartmentCode>MACS</DepartmentCode><institution>Swansea University</institution><apcterm>Other</apcterm><funders/><projectreference/><lastEdited>2025-10-20T11:45:32.4817334</lastEdited><Created>2025-10-20T11:17:08.2663807</Created><path><level id="1">Faculty of Science and Engineering</level><level id="2">School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering</level></path><authors><author><firstname>Murad</firstname><surname>Alabdullah</surname><order>1</order></author><author><firstname>Muhammad</firstname><surname>Elmessary</surname><orcid>0000-0001-9732-9010</orcid><order>2</order></author><author><firstname>Daniel</firstname><surname>Nagy</surname><order>3</order></author><author><firstname>N.</firstname><surname>Seoane</surname><orcid>0000-0003-0973-461x</orcid><order>4</order></author><author><firstname>A. J.</firstname><surname>Garc&#xED;a-Loureiro</surname><orcid>0000-0003-0574-1513</orcid><order>5</order></author><author><firstname>Karol</firstname><surname>Kalna</surname><orcid>0000-0002-6333-9189</orcid><order>6</order></author></authors><documents><document><filename>70729__35398__352b5e02f6834b8ea8af5183b7e0de7b.pdf</filename><originalFilename>70729.VoR.pdf</originalFilename><uploaded>2025-10-20T11:23:21.6672431</uploaded><type>Output</type><contentLength>5303573</contentLength><contentType>application/pdf</contentType><version>Version of Record</version><cronfaStatus>true</cronfaStatus><documentNotes>Copyright: 2024 The Authors. This work is licensed under a Creative Commons Attribution 4.0 License.</documentNotes><copyrightCorrect>true</copyrightCorrect><language>eng</language><licence>https://creativecommons.org/licenses/by/4.0/</licence></document></documents><OutputDurs/></rfc1807>
spelling 2025-10-20T11:45:32.4817334 v2 70729 2025-10-20 Scaling Challenges of Nanosheet Field-Effect Transistors Into Sub-2 nm Nodes d6f2e878d2e82c7f12a1e314a4ea07e5 Murad Alabdullah Murad Alabdullah true false 4be2e9acb658a7cabbc80ea75b6dfea8 0000-0001-9732-9010 Muhammad Elmessary Muhammad Elmessary true false f6efefac27b3523cc876c78741c44643 Daniel Nagy Daniel Nagy true false 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2025-10-20 MACS The scaling of nanosheet (NS) field effect transistors (FETs) from the 12 nm gate length to the ultimate gate length of 10 nm for sub-2 nm nodes brings additional technological challenges. Here, 3D finite element Monte Carlo simulations are employed to explore how to alter the NS architecture to increase the drive current ( IDD ) because the gate scaling to 10 nm results in a decline of the current (by 10.7 %). IDD of the 10 nm gate length NS FET will increase by 11% if the maximum n-type source/drain doping reaches 1×1020cm−3 , or increase by 3.8 % if the high- κ dielectric layer equivalent oxide thickness (EOT) is less than 1.0 nm. The reduction in the channel width below 40 nm or the reduction in the channel thickness below 5 nm will substantially decrease IDD. The sub-threshold figures of merit like the sub-threshold slope (SS) will decrease from 75 to 73 mV/dec, while the drain-induced barrier lowering (DIBL) will increase from 32 to 77 mV/V. Finally, the effect of strain to increase the drive current is strongly limited by quantum confinement. IDD will increase by 3% and by 14% in the 10 nm gate NS FET with the ⟨110⟩ and ⟨100⟩ channel orientations, respectively, when a strain of 0.5 % is applied to the channel, with a negligible increase for larger strain values ( 0.7 % and 1.0 %). Journal Article IEEE Journal of the Electron Devices Society 12 479 485 Institute of Electrical and Electronics Engineers (IEEE) 2168-6734 18 6 2024 2024-06-18 10.1109/jeds.2024.3416200 COLLEGE NANME Mathematics and Computer Science School COLLEGE CODE MACS Swansea University Other 2025-10-20T11:45:32.4817334 2025-10-20T11:17:08.2663807 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Murad Alabdullah 1 Muhammad Elmessary 0000-0001-9732-9010 2 Daniel Nagy 3 N. Seoane 0000-0003-0973-461x 4 A. J. García-Loureiro 0000-0003-0574-1513 5 Karol Kalna 0000-0002-6333-9189 6 70729__35398__352b5e02f6834b8ea8af5183b7e0de7b.pdf 70729.VoR.pdf 2025-10-20T11:23:21.6672431 Output 5303573 application/pdf Version of Record true Copyright: 2024 The Authors. This work is licensed under a Creative Commons Attribution 4.0 License. true eng https://creativecommons.org/licenses/by/4.0/
title Scaling Challenges of Nanosheet Field-Effect Transistors Into Sub-2 nm Nodes
spellingShingle Scaling Challenges of Nanosheet Field-Effect Transistors Into Sub-2 nm Nodes
Murad Alabdullah
Muhammad Elmessary
Daniel Nagy
Karol Kalna
title_short Scaling Challenges of Nanosheet Field-Effect Transistors Into Sub-2 nm Nodes
title_full Scaling Challenges of Nanosheet Field-Effect Transistors Into Sub-2 nm Nodes
title_fullStr Scaling Challenges of Nanosheet Field-Effect Transistors Into Sub-2 nm Nodes
title_full_unstemmed Scaling Challenges of Nanosheet Field-Effect Transistors Into Sub-2 nm Nodes
title_sort Scaling Challenges of Nanosheet Field-Effect Transistors Into Sub-2 nm Nodes
author_id_str_mv d6f2e878d2e82c7f12a1e314a4ea07e5
4be2e9acb658a7cabbc80ea75b6dfea8
f6efefac27b3523cc876c78741c44643
1329a42020e44fdd13de2f20d5143253
author_id_fullname_str_mv d6f2e878d2e82c7f12a1e314a4ea07e5_***_Murad Alabdullah
4be2e9acb658a7cabbc80ea75b6dfea8_***_Muhammad Elmessary
f6efefac27b3523cc876c78741c44643_***_Daniel Nagy
1329a42020e44fdd13de2f20d5143253_***_Karol Kalna
author Murad Alabdullah
Muhammad Elmessary
Daniel Nagy
Karol Kalna
author2 Murad Alabdullah
Muhammad Elmessary
Daniel Nagy
N. Seoane
A. J. García-Loureiro
Karol Kalna
format Journal article
container_title IEEE Journal of the Electron Devices Society
container_volume 12
container_start_page 479
publishDate 2024
institution Swansea University
issn 2168-6734
doi_str_mv 10.1109/jeds.2024.3416200
publisher Institute of Electrical and Electronics Engineers (IEEE)
college_str Faculty of Science and Engineering
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hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
document_store_str 1
active_str 0
description The scaling of nanosheet (NS) field effect transistors (FETs) from the 12 nm gate length to the ultimate gate length of 10 nm for sub-2 nm nodes brings additional technological challenges. Here, 3D finite element Monte Carlo simulations are employed to explore how to alter the NS architecture to increase the drive current ( IDD ) because the gate scaling to 10 nm results in a decline of the current (by 10.7 %). IDD of the 10 nm gate length NS FET will increase by 11% if the maximum n-type source/drain doping reaches 1×1020cm−3 , or increase by 3.8 % if the high- κ dielectric layer equivalent oxide thickness (EOT) is less than 1.0 nm. The reduction in the channel width below 40 nm or the reduction in the channel thickness below 5 nm will substantially decrease IDD. The sub-threshold figures of merit like the sub-threshold slope (SS) will decrease from 75 to 73 mV/dec, while the drain-induced barrier lowering (DIBL) will increase from 32 to 77 mV/V. Finally, the effect of strain to increase the drive current is strongly limited by quantum confinement. IDD will increase by 3% and by 14% in the 10 nm gate NS FET with the ⟨110⟩ and ⟨100⟩ channel orientations, respectively, when a strain of 0.5 % is applied to the channel, with a negligible increase for larger strain values ( 0.7 % and 1.0 %).
published_date 2024-06-18T05:28:51Z
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