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Spatial Sensitivity of Silicon GAA Nanowire FETs under Line Edge Roughness Variations
Guillermo Indalecio,
Antonio J. Garcia-Loureiro,
Muhammad A. Elmessary,
Karol Kalna ,
Natalia Seoane
IEEE Journal of the Electron Devices Society, Pages: 1 - 1
Swansea University Author: Karol Kalna
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DOI (Published version): 10.1109/JEDS.2018.2828504
Abstract
Standard analysis of variability sources in nanodevices lacks information about the spatial influence of the variability. However this spatial information is paramount for the industry and academia to improve the design of variability-resistant architectures. A recently developed technique, the Fluc...
Published in: | IEEE Journal of the Electron Devices Society |
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ISSN: | 2168-6734 |
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2018
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URI: | https://cronfa.swan.ac.uk/Record/cronfa39889 |
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<?xml version="1.0"?><rfc1807><datestamp>2018-07-30T10:42:40.3178095</datestamp><bib-version>v2</bib-version><id>39889</id><entry>2018-05-03</entry><title>Spatial Sensitivity of Silicon GAA Nanowire FETs under Line Edge Roughness Variations</title><swanseaauthors><author><sid>1329a42020e44fdd13de2f20d5143253</sid><ORCID>0000-0002-6333-9189</ORCID><firstname>Karol</firstname><surname>Kalna</surname><name>Karol Kalna</name><active>true</active><ethesisStudent>false</ethesisStudent></author></swanseaauthors><date>2018-05-03</date><deptcode>EEEG</deptcode><abstract>Standard analysis of variability sources in nanodevices lacks information about the spatial influence of the variability. However this spatial information is paramount for the industry and academia to improve the design of variability-resistant architectures. A recently developed technique, the Fluctuation Sensitivity Map (FSM) is used to analyse the spatial effect of the Line Edge Roughness (LER) variability in key figures-of-merit (FoM) in silicon Gate-All-Around (GAA) nanowire (NW) FETs. This technique gives insight about the local sensitivity identifying the regions inducing the strongest variability into the FoM. We analyse both 22 nm and 10 nm gate length GAA NW FETs affected by the LER with different amplitudes (0.6, 0.7, 0.85 nm) and correlation lengths (10, 20 nm) using in-house 3D quantum-corrected drift-diffusion simulation tool calibrated against experimental or Monte Carlo data. The FSM finds that the gate is the most sensitive region to LER deformations. We demonstrate that the specific location of the deformation inside the gate plays an important role in the performance and that the effect of the location is also dependent on the FoM analysed. Moreover, there is a negligible impact on the device performance if the LER deformation occurs in the source or drain region.</abstract><type>Journal Article</type><journal>IEEE Journal of the Electron Devices Society</journal><paginationStart>1</paginationStart><paginationEnd>1</paginationEnd><publisher/><issnElectronic>2168-6734</issnElectronic><keywords/><publishedDay>31</publishedDay><publishedMonth>12</publishedMonth><publishedYear>2018</publishedYear><publishedDate>2018-12-31</publishedDate><doi>10.1109/JEDS.2018.2828504</doi><url/><notes/><college>COLLEGE NANME</college><department>Electronic and Electrical Engineering</department><CollegeCode>COLLEGE CODE</CollegeCode><DepartmentCode>EEEG</DepartmentCode><institution>Swansea University</institution><apcterm/><lastEdited>2018-07-30T10:42:40.3178095</lastEdited><Created>2018-05-03T09:25:07.5694047</Created><path><level id="1">Faculty of Science and Engineering</level><level id="2">School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering</level></path><authors><author><firstname>Guillermo</firstname><surname>Indalecio</surname><order>1</order></author><author><firstname>Antonio J.</firstname><surname>Garcia-Loureiro</surname><order>2</order></author><author><firstname>Muhammad A.</firstname><surname>Elmessary</surname><order>3</order></author><author><firstname>Karol</firstname><surname>Kalna</surname><orcid>0000-0002-6333-9189</orcid><order>4</order></author><author><firstname>Natalia</firstname><surname>Seoane</surname><order>5</order></author></authors><documents><document><filename>0039889-03052018092729.pdf</filename><originalFilename>indalecio2018.pdf</originalFilename><uploaded>2018-05-03T09:27:29.9530000</uploaded><type>Output</type><contentLength>1607041</contentLength><contentType>application/pdf</contentType><version>Version of Record</version><cronfaStatus>true</cronfaStatus><embargoDate>2018-05-03T00:00:00.0000000</embargoDate><copyrightCorrect>true</copyrightCorrect><language>eng</language></document></documents><OutputDurs/></rfc1807> |
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2018-07-30T10:42:40.3178095 v2 39889 2018-05-03 Spatial Sensitivity of Silicon GAA Nanowire FETs under Line Edge Roughness Variations 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2018-05-03 EEEG Standard analysis of variability sources in nanodevices lacks information about the spatial influence of the variability. However this spatial information is paramount for the industry and academia to improve the design of variability-resistant architectures. A recently developed technique, the Fluctuation Sensitivity Map (FSM) is used to analyse the spatial effect of the Line Edge Roughness (LER) variability in key figures-of-merit (FoM) in silicon Gate-All-Around (GAA) nanowire (NW) FETs. This technique gives insight about the local sensitivity identifying the regions inducing the strongest variability into the FoM. We analyse both 22 nm and 10 nm gate length GAA NW FETs affected by the LER with different amplitudes (0.6, 0.7, 0.85 nm) and correlation lengths (10, 20 nm) using in-house 3D quantum-corrected drift-diffusion simulation tool calibrated against experimental or Monte Carlo data. The FSM finds that the gate is the most sensitive region to LER deformations. We demonstrate that the specific location of the deformation inside the gate plays an important role in the performance and that the effect of the location is also dependent on the FoM analysed. Moreover, there is a negligible impact on the device performance if the LER deformation occurs in the source or drain region. Journal Article IEEE Journal of the Electron Devices Society 1 1 2168-6734 31 12 2018 2018-12-31 10.1109/JEDS.2018.2828504 COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University 2018-07-30T10:42:40.3178095 2018-05-03T09:25:07.5694047 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Guillermo Indalecio 1 Antonio J. Garcia-Loureiro 2 Muhammad A. Elmessary 3 Karol Kalna 0000-0002-6333-9189 4 Natalia Seoane 5 0039889-03052018092729.pdf indalecio2018.pdf 2018-05-03T09:27:29.9530000 Output 1607041 application/pdf Version of Record true 2018-05-03T00:00:00.0000000 true eng |
title |
Spatial Sensitivity of Silicon GAA Nanowire FETs under Line Edge Roughness Variations |
spellingShingle |
Spatial Sensitivity of Silicon GAA Nanowire FETs under Line Edge Roughness Variations Karol Kalna |
title_short |
Spatial Sensitivity of Silicon GAA Nanowire FETs under Line Edge Roughness Variations |
title_full |
Spatial Sensitivity of Silicon GAA Nanowire FETs under Line Edge Roughness Variations |
title_fullStr |
Spatial Sensitivity of Silicon GAA Nanowire FETs under Line Edge Roughness Variations |
title_full_unstemmed |
Spatial Sensitivity of Silicon GAA Nanowire FETs under Line Edge Roughness Variations |
title_sort |
Spatial Sensitivity of Silicon GAA Nanowire FETs under Line Edge Roughness Variations |
author_id_str_mv |
1329a42020e44fdd13de2f20d5143253 |
author_id_fullname_str_mv |
1329a42020e44fdd13de2f20d5143253_***_Karol Kalna |
author |
Karol Kalna |
author2 |
Guillermo Indalecio Antonio J. Garcia-Loureiro Muhammad A. Elmessary Karol Kalna Natalia Seoane |
format |
Journal article |
container_title |
IEEE Journal of the Electron Devices Society |
container_start_page |
1 |
publishDate |
2018 |
institution |
Swansea University |
issn |
2168-6734 |
doi_str_mv |
10.1109/JEDS.2018.2828504 |
college_str |
Faculty of Science and Engineering |
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|
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facultyofscienceandengineering |
hierarchy_top_title |
Faculty of Science and Engineering |
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facultyofscienceandengineering |
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Faculty of Science and Engineering |
department_str |
School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering |
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active_str |
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description |
Standard analysis of variability sources in nanodevices lacks information about the spatial influence of the variability. However this spatial information is paramount for the industry and academia to improve the design of variability-resistant architectures. A recently developed technique, the Fluctuation Sensitivity Map (FSM) is used to analyse the spatial effect of the Line Edge Roughness (LER) variability in key figures-of-merit (FoM) in silicon Gate-All-Around (GAA) nanowire (NW) FETs. This technique gives insight about the local sensitivity identifying the regions inducing the strongest variability into the FoM. We analyse both 22 nm and 10 nm gate length GAA NW FETs affected by the LER with different amplitudes (0.6, 0.7, 0.85 nm) and correlation lengths (10, 20 nm) using in-house 3D quantum-corrected drift-diffusion simulation tool calibrated against experimental or Monte Carlo data. The FSM finds that the gate is the most sensitive region to LER deformations. We demonstrate that the specific location of the deformation inside the gate plays an important role in the performance and that the effect of the location is also dependent on the FoM analysed. Moreover, there is a negligible impact on the device performance if the LER deformation occurs in the source or drain region. |
published_date |
2018-12-31T03:50:44Z |
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1763752483972186112 |
score |
11.016235 |