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Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications / Olujide Adenekan; Paul Holland; Karol Kalna

Microelectronics Journal, Volume: 81, Pages: 94 - 100

Swansea University Author: Holland, Paul

  • Accepted Manuscript under embargo until: 28th September 2019

Abstract

The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental char...

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Published in: Microelectronics Journal
ISSN: 0026-2692
Published: 2018
Online Access: Check full text

URI: https://cronfa.swan.ac.uk/Record/cronfa44949
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Abstract: The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental characteristics of the SJ multi-gate MOSFET (SJ-MGFET) aiming at improving drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate variations in the device architecture and improve device performance by optimizing doping profile under charge imbalance. The SJ-MGFET, using a folded alternating U-shaped n/p– SJ drift region pillar width of 0.3 μm with a trench depth of 2.7 μm achieves specific on-resistance (Ron,sp) of 0.21 mΩ.cm2 at a BV of 65 V. In comparison with conventional planar gate SJ-LDMOSFETs, the optimised SJ-MGFET gives 68% reduction in Ron,sp and 41% increase in a saturation drain current at a drain voltage of 5 V and a gate voltage of 10 V.
Keywords: Super-junction (SJ), Multi-gate (MG), Power MOSFETs, Silicon-on-insulator (SOI), Breakdown voltage (BV), Specific on-resistance
College: College of Engineering
Start Page: 94
End Page: 100