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Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications / Paul, Holland; Karol, Kalna

Microelectronics Journal, Volume: 81, Pages: 94 - 100

Swansesa University Authors: Paul, Holland, Karol, Kalna

Abstract

The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental char...

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Published in: Microelectronics Journal
ISSN: 0026-2692
Published: 2018
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URI: https://cronfa.swan.ac.uk/Record/cronfa44949
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first_indexed 2018-10-18T13:20:32Z
last_indexed 2018-11-26T14:20:46Z
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spelling 2018-11-26T12:46:53.0590923 v2 44949 2018-10-18 Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications 9c7eea4ea9d615fcbf2801a672dd2e7f Paul Holland Paul Holland true false 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2018-10-18 EEN The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental characteristics of the SJ multi-gate MOSFET (SJ-MGFET) aiming at improving drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate variations in the device architecture and improve device performance by optimizing doping profile under charge imbalance. The SJ-MGFET, using a folded alternating U-shaped n/p– SJ drift region pillar width of 0.3 μm with a trench depth of 2.7 μm achieves specific on-resistance (Ron,sp) of 0.21 mΩ.cm2 at a BV of 65 V. In comparison with conventional planar gate SJ-LDMOSFETs, the optimised SJ-MGFET gives 68% reduction in Ron,sp and 41% increase in a saturation drain current at a drain voltage of 5 V and a gate voltage of 10 V. Journal Article Microelectronics Journal 81 94 100 0026-2692 Super-junction (SJ), Multi-gate (MG), Power MOSFETs, Silicon-on-insulator (SOI), Breakdown voltage (BV), Specific on-resistance 31 12 2018 2018-12-31 10.1016/j.mejo.2018.09.007 COLLEGE NANME Engineering COLLEGE CODE EEN Swansea University 2018-11-26T12:46:53.0590923 2018-10-18T10:13:20.0144613 College of Engineering Engineering Olujide Adenekan 1 Paul Holland 2 Karol Kalna 0000-0002-6333-9189 3 0044949-19102018083129.pdf adenekan2018v2.pdf 2018-10-19T08:31:29.6030000 Output 1620853 application/pdf Accepted Manuscript true 2019-09-28T00:00:00.0000000 true eng
title Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications
spellingShingle Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications
Paul, Holland
Karol, Kalna
title_short Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications
title_full Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications
title_fullStr Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications
title_full_unstemmed Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications
title_sort Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications
author_id_str_mv 9c7eea4ea9d615fcbf2801a672dd2e7f
1329a42020e44fdd13de2f20d5143253
author_id_fullname_str_mv 9c7eea4ea9d615fcbf2801a672dd2e7f_***_Paul, Holland
1329a42020e44fdd13de2f20d5143253_***_Karol, Kalna
author Paul, Holland
Karol, Kalna
format Journal article
container_title Microelectronics Journal
container_volume 81
container_start_page 94
publishDate 2018
institution Swansea University
issn 0026-2692
doi_str_mv 10.1016/j.mejo.2018.09.007
college_str College of Engineering
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hierarchy_top_id collegeofengineering
hierarchy_top_title College of Engineering
hierarchy_parent_id collegeofengineering
hierarchy_parent_title College of Engineering
department_str Engineering{{{_:::_}}}College of Engineering{{{_:::_}}}Engineering
document_store_str 1
active_str 0
description The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental characteristics of the SJ multi-gate MOSFET (SJ-MGFET) aiming at improving drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate variations in the device architecture and improve device performance by optimizing doping profile under charge imbalance. The SJ-MGFET, using a folded alternating U-shaped n/p– SJ drift region pillar width of 0.3 μm with a trench depth of 2.7 μm achieves specific on-resistance (Ron,sp) of 0.21 mΩ.cm2 at a BV of 65 V. In comparison with conventional planar gate SJ-LDMOSFETs, the optimised SJ-MGFET gives 68% reduction in Ron,sp and 41% increase in a saturation drain current at a drain voltage of 5 V and a gate voltage of 10 V.
published_date 2018-12-31T04:06:44Z
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score 10.735779