Conference Paper/Proceeding/Abstract 388 views 100 downloads
3D Monte Carlo Simulations of n-type Nanowire-FETs: The Effect of Gate Scaling
2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD), Pages: 1 - 4
Swansea University Authors:
Murad Alabdullah, Karol Kalna
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DOI (Published version): 10.1109/smacd65553.2025.11092079
Abstract
The potential of gate-all-around (GAA) nanowire (NW) field-effect transistors (FETs) to replace sub-3 nm complementary metal-oxide-semiconductor (CMOS) technology has attracted significant interest. This simulation study investigates the impact of gate length (LG) scaling on the drain drive current...
| Published in: | 2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD) |
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| ISBN: | 979-8-3315-2396-1 979-8-3315-2395-4 |
| ISSN: | 2575-4874 2575-4890 |
| Published: |
IEEE-Xplore, Istanbul, Turkiye
IEEE
2025
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| Online Access: |
Check full text
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| URI: | https://cronfa.swan.ac.uk/Record/cronfa70139 |
| Abstract: |
The potential of gate-all-around (GAA) nanowire (NW) field-effect transistors (FETs) to replace sub-3 nm complementary metal-oxide-semiconductor (CMOS) technology has attracted significant interest. This simulation study investigates the impact of gate length (LG) scaling on the drain drive current (IDD) in NW-FETs using an advanced in-house 3D finite-element ensemble Monte Carlo (MC) simulation toolbox that incorporates quantum corrections via the Schrodinger equation. The MC simulated ID-VG characteristics show excellent agreement with experimental data across both low and high drain biases. Our results reveal that scaling the gate length down to 10 nm leads to an unexpected decline in IDD beyond 16 nm. While IDD initially increases from 22 nm to 16 nm, consistent with scaling theory, it subsequently decreases by up to 12% at 10 nm. This reduction is attributed to intensified back scattering and enhanced fringing electric fields resulting from the shorter source-to-drain distance. This study uniquely demonstrates the critical role of these effects in limiting drive current at sub-16 nm gate lengths in NW-FETs—providing predictive insight into non-ideal shortchannel transport behaviors and highlighting key challenges for performance optimization in future transistor architectures. |
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| Keywords: |
Performance evaluation, Three-dimensional displays, Monte Carlo methods, Gallium arsenide, Potential well, Logic gates, Threshold voltage, Electric fields, Optimization, Electrons |
| College: |
Faculty of Science and Engineering |
| Start Page: |
1 |
| End Page: |
4 |