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3D Monte Carlo Simulations of n-type Nanowire-FETs: The Effect of Gate Scaling

Murad Alabdullah, N. Seoane, A. J. García-Loureiro, Karol Kalna Orcid Logo

2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD), Pages: 1 - 4

Swansea University Authors: Murad Alabdullah, Karol Kalna Orcid Logo

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DOI (Published version): 10.1109/smacd65553.2025.11092079

Abstract

The potential of gate-all-around (GAA) nanowire (NW) field-effect transistors (FETs) to replace sub-3 nm complementary metal-oxide-semiconductor (CMOS) technology has attracted significant interest. This simulation study investigates the impact of gate length (LG) scaling on the drain drive current...

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Published in: 2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD)
ISBN: 979-8-3315-2396-1 979-8-3315-2395-4
ISSN: 2575-4874 2575-4890
Published: IEEE-Xplore, Istanbul, Turkiye IEEE 2025
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URI: https://cronfa.swan.ac.uk/Record/cronfa70139
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last_indexed 2026-01-28T05:33:37Z
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spelling 2026-01-27T11:10:44.5104047 v2 70139 2025-08-08 3D Monte Carlo Simulations of n-type Nanowire-FETs: The Effect of Gate Scaling d6f2e878d2e82c7f12a1e314a4ea07e5 Murad Alabdullah Murad Alabdullah true false 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2025-08-08 MACS The potential of gate-all-around (GAA) nanowire (NW) field-effect transistors (FETs) to replace sub-3 nm complementary metal-oxide-semiconductor (CMOS) technology has attracted significant interest. This simulation study investigates the impact of gate length (LG) scaling on the drain drive current (IDD) in NW-FETs using an advanced in-house 3D finite-element ensemble Monte Carlo (MC) simulation toolbox that incorporates quantum corrections via the Schrodinger equation. The MC simulated ID-VG characteristics show excellent agreement with experimental data across both low and high drain biases. Our results reveal that scaling the gate length down to 10 nm leads to an unexpected decline in IDD beyond 16 nm. While IDD initially increases from 22 nm to 16 nm, consistent with scaling theory, it subsequently decreases by up to 12% at 10 nm. This reduction is attributed to intensified back scattering and enhanced fringing electric fields resulting from the shorter source-to-drain distance. This study uniquely demonstrates the critical role of these effects in limiting drive current at sub-16 nm gate lengths in NW-FETs—providing predictive insight into non-ideal shortchannel transport behaviors and highlighting key challenges for performance optimization in future transistor architectures. Conference Paper/Proceeding/Abstract 2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD) 0 1 4 IEEE IEEE-Xplore, Istanbul, Turkiye 979-8-3315-2396-1 979-8-3315-2395-4 2575-4874 2575-4890 Performance evaluation, Three-dimensional displays, Monte Carlo methods, Gallium arsenide, Potential well, Logic gates, Threshold voltage, Electric fields, Optimization, Electrons 29 7 2025 2025-07-29 10.1109/smacd65553.2025.11092079 COLLEGE NANME Mathematics and Computer Science School COLLEGE CODE MACS Swansea University Not Required 2026-01-27T11:10:44.5104047 2025-08-08T12:31:01.4312475 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Murad Alabdullah 1 N. Seoane 2 A. J. García-Loureiro 3 Karol Kalna 0000-0002-6333-9189 4 70139__35133__9235be0723634f928323a4668804aa4d.pdf 70139.AAM.pdf 2025-09-18T16:15:34.7544724 Output 1806790 application/pdf Accepted Manuscript true Author accepted manuscript document released under the terms of a Creative Commons CC-BY licence using the Swansea University Research Publications Policy (rights retention). true eng https://creativecommons.org/licenses/by/4.0/deed.en
title 3D Monte Carlo Simulations of n-type Nanowire-FETs: The Effect of Gate Scaling
spellingShingle 3D Monte Carlo Simulations of n-type Nanowire-FETs: The Effect of Gate Scaling
Murad Alabdullah
Karol Kalna
title_short 3D Monte Carlo Simulations of n-type Nanowire-FETs: The Effect of Gate Scaling
title_full 3D Monte Carlo Simulations of n-type Nanowire-FETs: The Effect of Gate Scaling
title_fullStr 3D Monte Carlo Simulations of n-type Nanowire-FETs: The Effect of Gate Scaling
title_full_unstemmed 3D Monte Carlo Simulations of n-type Nanowire-FETs: The Effect of Gate Scaling
title_sort 3D Monte Carlo Simulations of n-type Nanowire-FETs: The Effect of Gate Scaling
author_id_str_mv d6f2e878d2e82c7f12a1e314a4ea07e5
1329a42020e44fdd13de2f20d5143253
author_id_fullname_str_mv d6f2e878d2e82c7f12a1e314a4ea07e5_***_Murad Alabdullah
1329a42020e44fdd13de2f20d5143253_***_Karol Kalna
author Murad Alabdullah
Karol Kalna
author2 Murad Alabdullah
N. Seoane
A. J. García-Loureiro
Karol Kalna
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doi_str_mv 10.1109/smacd65553.2025.11092079
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description The potential of gate-all-around (GAA) nanowire (NW) field-effect transistors (FETs) to replace sub-3 nm complementary metal-oxide-semiconductor (CMOS) technology has attracted significant interest. This simulation study investigates the impact of gate length (LG) scaling on the drain drive current (IDD) in NW-FETs using an advanced in-house 3D finite-element ensemble Monte Carlo (MC) simulation toolbox that incorporates quantum corrections via the Schrodinger equation. The MC simulated ID-VG characteristics show excellent agreement with experimental data across both low and high drain biases. Our results reveal that scaling the gate length down to 10 nm leads to an unexpected decline in IDD beyond 16 nm. While IDD initially increases from 22 nm to 16 nm, consistent with scaling theory, it subsequently decreases by up to 12% at 10 nm. This reduction is attributed to intensified back scattering and enhanced fringing electric fields resulting from the shorter source-to-drain distance. This study uniquely demonstrates the critical role of these effects in limiting drive current at sub-16 nm gate lengths in NW-FETs—providing predictive insight into non-ideal shortchannel transport behaviors and highlighting key challenges for performance optimization in future transistor architectures.
published_date 2025-07-29T05:32:05Z
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